IC Packaging Technologist at Astera Labs

Santa Clara, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

SemiconductorsIndustries

Requirements

M.S. or Ph.D. in Electrical Engineering, Materials Science, or related discipline
10 years of experience in IC packaging development with deep exposure to SIPI and 2.5D/3D integration technologies
Hands-on experience with CoWoS, interposers, WLP, chiplet-based integration
Proficiency in SIPI tools: HFSS, Siwave, ADS, HSPICE, etc
Hands-on experience in high-frequency measurement and characterization with tools such as VNA
Expert knowledge of EDA design tools: Cadence Allegro/APD, Altium, etc
Entrepreneurial, open-mind behavior and hands-on work ethic with the ability to prioritize a dynamic list of multiple tasks
Proven experience in end-to-end IC packaging development for advanced packaging: CoWoS, interposers, WLP, chiplet-based integration
Experience in high-speed SerDes IC package development, including interfaces such as PCI Express (PCIe) Gen4/Gen5/Gen6, CXL (Compute Express Link), and other multi-gigabit transceiver protocols, as well as devices such as retimers, switches, and PHYs operating at data rates up to 224G PAM4 and beyond
Strong background in package SIPI for ultra-high-speed interfaces (up to 448G), including: SERDES, Ethernet, DDR, Die-to-Die (e.g., BoW or UCIe)
Demonstrated success leading die-package-board co-design efforts, including packaging platform selection, stack-up and structure definition, signal and power integrity (SIPI) optimization, design for manufacturability (DFM), and driving designs through tape-out to volume manufacturing
Hands-on lab validation experience and simulation-correlation with high-frequency measurement (e.g., VNA, TDR)
Extensive engagement with foundries (e.g., TSMC), OSATs, and substrate suppliers for collaborative package technology development
Deep understanding of the technology landscape, cost drivers, and market trends influencing IC packaging innovation
Demonstrated ability to operate cross-functionally across design, product/test engineering, operations, reliability, marketing, and customer-facing engineering teams
Exceptional technical collaboration with silicon design teams to define chip-to-chip integration flows, accounting for timing, power delivery, and physical package layout alternatives
Knowledge of mechanical, thermal, and electrical design trade-offs in package development (preferred)

Responsibilities

Lead and innovate in the development of high-performance, high-speed, and advanced IC package solutions
Contribute to strategic roadmap execution and deliver package solutions into production

Skills

Key technologies and capabilities for this role

IC Packaging2.5D/3D IntegrationSIPICoWoSInterposersWLPChiplet IntegrationHFSSSiwaveADSHSPICEVNACadence AllegroAltium

Questions & Answers

Common questions about this position

What salary can I expect for the IC Packaging Technologist role?

This information is not specified in the job description.

Is this IC Packaging Technologist position remote or onsite?

This information is not specified in the job description.

What are the key skills required for the IC Packaging Technologist role?

The role requires an M.S. or Ph.D. in Electrical Engineering, Materials Science, or related field, 10 years of IC packaging experience with SIPI and 2.5D/3D integration, hands-on experience with CoWoS, interposers, WLP, and chiplets, proficiency in SIPI tools like HFSS and Siwave, and expertise in EDA tools like Cadence Allegro.

What is the company culture like at Astera Labs?

Astera Labs emphasizes innovation, trusted relationships with hyperscalers, and a flexible, interoperable approach to connectivity solutions for AI and cloud infrastructure.

What makes a strong candidate for the IC Packaging Technologist position?

A strong candidate has proven end-to-end experience in advanced IC packaging like CoWoS and chiplets, expertise in high-speed SerDes for PCIe and CXL up to 448G, success in die-package-board co-design, and an entrepreneurial, hands-on work ethic.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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