Sr. Physical Design Engineer

Position Overview

The Physical Design Engineer will be responsible for block level synthesis, place & route, and sign-off.

Mission

To deliver fast, efficient AI inference through advanced LPU-based systems.

Responsibilities & Opportunities

• Responsible for block level Synthesis, Place & Route, Timing Sign-off, Physical & Electrical Sign Off, Logical Equivalence, and Low-Power checks - end-to-end RTL to GDS at block level.
• Responsible for floorplanning, IP placement, timing constraints, and UPF.
• Collaborate closely with the Microarchitecture/Logic Design team to optimize the design for best PPA (Power, Performance, Area) goals.
• Work with the Infrastructure/EDA/CAD team to optimize flows and methodology. Influence tools, flows, and physical design methodology with a data-driven approach to optimize flows for best PPA.
• Work closely with vendor teams to achieve various milestone goals for block-level physical implementation.

Ideal Candidates Have/Are

• Education: BS in Electrical Engineering or Computer Engineering or related degree required; advanced degrees (MS, PhD) are a plus.
• Experience: 5-8 years of meaningful industry experience and a background in block/top-level physical design of high-speed processors (i.e., Graphics, Microprocessors, Network Processors, or Mobile / Multimedia SOCs).
• Technical Skills:
  • Proven track record of implementing designs through synthesis, placement, CTS, Routing, Extraction, Timing, and Physical/Electrical Verification.
  • Good knowledge of employing best-known methods to handle/optimize DFT structures in Physical Design at the block level.
  • Strong hands-on experience in implementing multi-voltage, multi-clock domain designs.
  • Proficiency in different CTS methodologies and global clock design.
  • Expert in implementing PD power optimization techniques and having a keen eye for power reduction options throughout the PD cycle.
  • Strong understanding of timing constraints & analysis, power grid design, power analysis (EMIR/di/dt), ECO generation, and MCMM STA.
  • Deep understanding of low-power formats like UPF/CPF.
  • Experience in formal equivalency checks and Low Power Rule verification.
  • Expertise in industry-standard EDA tools like Cadence Genus/Innovus/Tempus, Synopsys Fusion Compiler/ICC2/Primetime, Ansys Redhawk, Joules/PTPX.
  • Strong Automation skills using scripting languages like TCL, Python, Perl, etc.

About Groq

Groq delivers fast, efficient AI inference. Our LPU-based system powers GroqCloud™, giving businesses and developers the speed and scale they need. Headquartered in Silicon Valley, we are on a mission to make high-performance AI compute more accessible and affordable. When real-time AI is within reach, anything is possible. Build fast.

Attributes of a Groqster

• Humility: Egos are checked at the door.
• Collaborative & Team Savvy: We make up the smartest person in the room, together.
• Growth & Giver Mindset: Learn it all versus know it all, we share knowledge generously.
• Curious & Innovative: Take a creative approach to projects, problems, and design.
• Passion, Grit, & Boldness: No-limit thinking, fueling informed risk-taking.

Compensation

• Salary Range: $169,915 - $199,900 (determined by skills, qualifications, experience, and internal benchmarks).
• Package: Competitive base salary, equity, and benefits.

Location

Some roles may require being located near or on our primary sites, as indicated in the job description.

Company Information

At Groq, our goal is to hire and promote an exceptional workforce as diverse as the global populations we serve. Groq is an equal opportunity employer committed to diversity, inclusion, and belonging in all aspects of our organization. We value and celebrate diversity in thought, beliefs, talent, expression, and backgrounds. We know that our individual differences make us better.