Sr. Physical Design Engineer

Palo Alto, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

Candidates must possess a BS in Electrical Engineering or Computer Engineering, with advanced degrees being a plus, and have 5-8 years of relevant industry experience in the physical design of high-speed processors. A proven track record in synthesis, placement, CTS, routing, extraction, timing, and physical/electrical verification is essential, along with strong knowledge of DFT structures and multi-voltage/multi-clock domain designs. Proficiency in CTS methodologies, global clock design, PD power optimization techniques, timing constraints and analysis, power grid design, power analysis (EMIR/di/dt), ECO generation, MCMM STA, UPF/CPF, formal equivalency checks, and low power rule verification is required. Expertise in EDA tools such as Cadence Genus/Innovus/Tempus, Synopsys Fusion Compiler/ICC2/Primetime, and Ansys Redhawk/Joules/PTPX, along with strong automation skills in TCL, Python, or Perl, is also necessary.

Responsibilities

The Physical Design Engineer is responsible for end-to-end RTL to GDS at the block level, including synthesis, place & route, timing sign-off, physical & electrical sign-off, logical equivalence, and low-power checks. This role involves floorplanning, IP placement, timing constraints, and UPF management. The engineer will collaborate with Microarchitecture/Logic Design teams for PPA optimization, work with Infrastructure/EDA/CAD teams to enhance flows and methodology, and engage with vendor teams to meet block-level physical implementation milestones.

Skills

Physical Design

Synthesis

Place & Route

Timing Sign-off

Physical Verification

Electrical Verification

Logical Equivalence

Low-Power Checks

RTL to GDS

Floorplanning

IP Placement

Timing Constraints

UPF

PPA Optimization

DFT

Multi-voltage Designs

Multi-clock Domain Designs

High-speed Processors

Groq

AI inference technology for scalable solutions

About Groq

Groq specializes in AI inference technology, providing the Groq LPU™, which is known for its high compute speed, quality, and energy efficiency. The Groq LPU™ is designed to handle AI processing tasks quickly and effectively, making it suitable for both cloud and on-premises applications. Unlike many competitors, Groq's products are designed, fabricated, and assembled in North America, which helps maintain high standards of quality and performance. The company targets a variety of clients across different industries that require fast and efficient AI processing capabilities. Groq's goal is to deliver scalable AI inference solutions that meet the growing demands for rapid data processing in the AI and machine learning market.

Mountain View, CaliforniaHeadquarters

2016Year Founded

$1,266.5MTotal Funding

SERIES_DCompany Stage

AI & Machine LearningIndustries

201-500Employees

Benefits

Remote Work Options

Company Equity

Risks

Increased competition from SambaNova Systems and Gradio in high-speed AI inference.

Geopolitical risks in the MENA region may affect the Saudi Arabia data center project.

Rapid expansion could strain Groq's operational capabilities and supply chain.

Differentiation

Groq's LPU offers exceptional compute speed and energy efficiency for AI inference.

The company's products are designed and assembled in North America, ensuring high quality.

Groq emphasizes deterministic performance, providing predictable outcomes in AI computations.

Upsides

Groq secured $640M in Series D funding, boosting its expansion capabilities.

Partnership with Aramco Digital aims to build the world's largest inferencing data center.

Integration with Touchcast's Cognitive Caching enhances Groq's hardware for hyper-speed inference.

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