Technical Chief of Staff for ASIC Engineering at Astera Labs

San Jose, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, AI InfrastructureIndustries

Requirements

10+ years in semiconductor/SoC/ASIC or adjacent high-complexity engineering environment (e.g., CPU/IP/System companies)
Proven success in Chief of Staff, Staff Program Manager, TPM Director, or similar technical leadership-enablement role
Strong technical acumen — able to understand engineering trade-offs and make decisions with limited information, challenge assumptions, and earn credibility with senior ICs
Demonstrated experience running program cadence for complex silicon programs (tapeout, IP integration, etc.)
Proven ability to organize complex work

Responsibilities

Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs
Frame and resolve high-leverage decisions — proactively surface blockers (technical, operational, organizational) before they escalate
Manage escalations and organizational friction — diagnose root causes, coordinate resolution paths, and ensure durable fixes
Partner cross-functionally with Hardware, Product, and Quality teams to ensure clarity of communication, alignment on priorities, and disciplined follow-through on decisions
Support org design, headcount planning, and hiring prioritization for engineering teams
Maintain alignment across functions through clear messaging and communication, validate existence and validation of processes
Navigate org dynamics, build trust, and constructively challenge assumptions; maintain psychological safety
Support the head of engineering with administrative and org related activities
Status management — collect and track status across functions contributing to ASIC tapeouts
Milestone tracking — maintain methodology checklists and boundary agreements to ensure schedule adherence
IP and vendor tracking — own visibility into IP deliveries, version inventory, vendor issues, and escalation loops
Quality & documentation — monitor quality KPIs, ensure engineering documentation completeness
Requirements tracking — ensure PRDs/features are captured, tracked, baselined
Resource monitoring — track compute, hardware, storage consumption and thresholds
Internal reporting — generate status reporting for Silicon Engineering leadership
Drive cross-engineering outcomes through credibility, clarity, and follow-through — not hierarchy
Create order in ambiguous spaces; shape scope where it is undefined

Skills

ASIC Engineering

Silicon Engineering

CXL

PCIe

Ethernet

Program Management

Org Design

Headcount Planning

Cross-functional Collaboration

Operational Cadence

Problem-solving

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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