Substrate IC Package Layout Design Engineer at Etched.ai

San Jose, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, AIIndustries

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
10+ years of experience in IC substrate layout design for high-performance processors or accelerators
Extensive experience with large substrate packages (>50mm) and complex high-density layouts
Proven experience with high-power (700W+) package designs and robust power delivery networks
Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches)
Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer designs

Responsibilities

Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators
Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements
Ensure robust power delivery designs capable of supporting >700W custom silicon solutions
Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues
Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout
Optimize CoWoS interposer designs for thermal and electrical performance
Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs
Develop and maintain design documentation and guidelines for future substrate designs
Support design reviews and provide technical guidance to junior team members

Skills

Key technologies and capabilities for this role

IC Substrate Layout DesignCoWoS IntegrationPower Delivery NetworksHigh-Speed SignalingSignal IntegrityPower IntegrityLarge Substrate DesignMulti-layer SubstrateHigh Pin Count RoutingDense Routing

Questions & Answers

Common questions about this position

What is the salary for this Substrate IC Package Layout Design Engineer position?

Salary information not provided.

Is this role remote or onsite?

This is an onsite position.

What are the key skills required for this role?

The role requires 10+ years of experience in IC substrate layout design for high-performance processors or accelerators, extensive experience with large substrate packages (>50mm), proven experience with high-power (700W+) package designs, expertise in high-speed signaling (>50GHz), and strong experience with CoWoS interposer designs.

What is the company culture like at Etched.ai?

This information is not specified in the job description.

What makes a strong candidate for this position?

A strong candidate has a Bachelor’s or Master’s in Electrical Engineering or related field, plus 10+ years in IC substrate layout design, with expertise in large substrates (>50mm), high-power delivery (700W+), high-speed signaling (>50GHz), and CoWoS integration.

Etched.ai

Develops servers for transformer inference

About Etched.ai

The company specializes in developing powerful servers for transformer inference, utilizing transformer architecture integrated into their chips to achieve highly efficient and advanced technology. The main technologies used in the product are transformer architecture and advanced chip integration.

Cupertino, CA, USAHeadquarters

2022Year Founded

$5.4MTotal Funding

SEEDCompany Stage

HardwareIndustries

11-50Employees