Post Silicon Validation Engineer
GroqFull Time
Mid-level (3 to 4 years), Senior (5 to 8 years)
Key technologies and capabilities for this role
Common questions about this position
A minimum of 10-12 years of ATE experience developing test programs for server, client/mobile, or HPC products is required.
Candidates need hands-on experience with ATE test equipment like Advantest SMT8 (preferred), writing Scan/Mbist/PHY tests, developing product binning methods, and secure manufacturing flows, plus strong understanding of hardware design requirements including CPM/IBIS models and SI/PI simulation.
A Bachelor’s or Master’s Degree in a technical subject area is required.
Excellent problem-solving skills, written and verbal communication, organization skills, and being highly self-motivated are required.
Prior DfT experience is highly desired.
Develops custom RISC-V server solutions
Rivos develops high-performance and power-efficient server solutions using RISC-V, an open-source hardware instruction set architecture. Their custom hardware is designed to meet the specific needs of enterprise clients, including data centers and cloud service providers, who require reliable systems for extensive data processing and storage. Rivos stands out in the competitive server market by utilizing RISC-V technology, which allows for greater flexibility and customization compared to traditional proprietary solutions. This enables Rivos to offer tailored and cost-effective products. The company generates revenue by selling specialized servers and may also provide related services like hardware support and consulting. Rivos aims to address the unique demands of high-performance computing environments while ensuring security and efficiency.