Responsibilities

The Senior Layout PCB Engineer will lead the design and optimization of high-speed PCB layouts using Cadence Allegro for 100G signaling. Responsibilities include implementing strategies for impedance matching, trace routing, and crosstalk mitigation to ensure robust designs. The engineer will develop and implement power distribution networks for high-performance data center hardware, designing power planes, decoupling strategies, and thermal management solutions. Additionally, they will manage the design of complex HDI PCB stack-ups for multi-layer boards, integrating blind/buried vias and microvias to enhance signal integrity. Collaboration with electrical and mechanical engineering teams will be necessary to integrate PCB designs within the overall system architecture, providing input during design reviews to optimize performance and manufacturability.