Principal Test Engineer at Astera Labs

San Jose, California, United States

Apply Now

Not SpecifiedCompensation

Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, AIIndustries

Requirements

Strong academic and technical background in electrical engineering (minimum Bachelor’s in EE required, Master’s preferred)
≥8 years of experience releasing complex SoC/silicon products to high volume manufacturing
Working knowledge of high-speed protocols like PCIe (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc
Professional attitude with ability to execute on multiple tasks with minimal supervision
Strong team player with good communication skills to work alongside a team of high caliber engineers
Entrepreneurial, open-minded behavior and can-do attitude
Hands-on experience with high-speed mixed signal SoC test program/hardware development on multiple high-speed test platforms
Experience collaborating with design team to define test strategy, create and own test plan
Experience with tester platform selection, design, and development of ATE hardware for wafer sort and final test
Familiarity with high-speed load board design techniques
Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality
Strong knowledge and development of DFT techniques (SCAN, MEMBIST, SerDes and other functional tests)
Skilled in control interfaces – I2C, I3C, SPI, MDIO, JTAG etc
Expertise in production test of high speed SerDes operating at 16Gbps and higher
Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug
Experience with lab equipment including protocol analyzers and oscilloscopes
Experience with using Advantest 93k ATE platform
Proficiency in at least one modern programming language such as C/C++, Python

Responsibilities

Develop and oversee SoC test strategy
Interact with manufacturing partners
Define and implement ATE programs
Own the product from design, initial samples through high volume production ramp
Lead ATE Test solutions for complex mixed-signal silicon SoC products
Collaborate with design team to define test strategy, create and own test plan

Skills

Key technologies and capabilities for this role

PCIeEthernetInfinibandDDRNVMeUSBATESoC TestingMixed-Signal TestingTest StrategyHigh-Volume ManufacturingHigh-Speed Protocols

Questions & Answers

Common questions about this position

What education is required for the Principal Test Engineer role?

A Bachelor’s in Electrical Engineering is required at minimum, with a Master’s preferred.

What experience level is needed for this position?

Candidates need ≥8 years of experience releasing complex SoC/silicon products to high volume manufacturing.

What key technical skills are required?

Required skills include hands-on experience with high-speed mixed-signal SoC test program/hardware development, knowledge of protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, expertise in ATE programming with Advantest 93k, and proficiency in C/C++ or Python.

What soft skills or personal qualities are they looking for?

They seek a professional attitude with ability to execute multiple tasks with minimal supervision, strong team player with good communication skills, and an entrepreneurial, open-minded behavior with a can-do attitude.

What makes a strong candidate for this Principal Test Engineer role?

A strong candidate has proven experience leading ATE test solutions for complex mixed-signal SoC products, collaboration with design teams on test strategy, expertise in high-speed SerDes testing at 16Gbps+, and a track record of optimizing ATE test time while ensuring quality.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

Land your dream remote job 3x faster with AI

Try Jobo Free