Lead Package Design Engineer at Astera Labs

San Jose, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

BS/MS in Engineering (Electrical, Mechanical, Materials Science, Physics, or related field)
6+ years of experience in Cadence APD/SiP with a track record of independently designing and releasing FCBGA/FCCSP packages from concept to tape-out
Proven experience leading package design efforts, reviewing and mentoring other designers, and setting technical directions
Deep understanding of BGA substrate technologies, stackups, design rules, and assembly processes
Familiarity with package reliability, SI/PI, and design sign-off methodologies
Entrepreneurial, open-minded, and hands-on work ethic with the ability to drive multiple priorities in a dynamic environment
Strong collaboration and communication skills to work effectively across functions and influence outcomes
Expert proficiency in Cadence APD/SiP (must have); able to design large-body BGAs from concept through tape-out with minimal guidance
Strong knowledge of package BOM integration, layer stackup, padstacks, constraint setup (physical and electrical), SMT component design, and optimization based on SI/PI feedback
Experience running and interpreting DRC/DRV/LVS/DFM checks, generating documentation, and releasing Gerbers/artwork
Ability to conduct feasibility studies such as fan-out, mock-ups, and layer/package size reduction
Understanding of package manufacturing flow, supply chain considerations, reliability, and risk management
Technical leadership in driving new APD design flows, methodologies, and automation (working with vendors or through scripting)
Multi-chip, interposer, 2.5D or heterogeneous package design experience (preferred)
Proficiency in scripting languages for design and reporting automation (preferred)

Responsibilities

Take ownership of package design and layout for Astera Labs’ portfolio of connectivity products
Drive package substrate design from definition to tape-out, including performance optimization, design for manufacturing, and sign-off verification
Provide technical guidance within the package design team: mentoring junior designers, guiding best practices in APD, reviewing design work for quality and consistency
Work closely with SI/PI, product engineering, and hardware teams to ensure first-pass success
Help shape design flows, champion productivity improvements
Represent package design expertise in cross-functional discussions

Skills

Cadence APD

IC Package Design

Package Layout

SI/PI

ASIC Packaging

Substrate Design

DFM

Sign-off Verification

Signal Integrity

Power Integrity

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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