Soc Architect - Memory Subsystem at Samsung Research America

The position is onsite.

This information is not specified in the job description.

Candidates need 10+ years in SOC or ASIC design and architecture, over 7 years direct experience in Fabric, System Cache, or DRAM controller architecture or microarchitecture, understanding of memory controller architecture including scheduling, prioritization and QoS, and detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB). A BSc, Masters, or PhD in Computer Science/Engineering or equivalent is required.

The lab focuses on innovative SoC architecture, bus/memory subsystems, and IP blocks for Samsung Galaxy products, collaborating with global partners, Samsung MX headquarters, and R&D teams to develop high-performance SoCs for smartphones, tablets, and future devices.

A strong candidate will have 10+ years of SOC/ASIC experience with over 7 years specifically in Fabric, System Cache, or DRAM controller architecture, plus expertise in memory controllers and ARM bus protocols, along with advanced education in Computer Science/Engineering.