Silicon Power Engineer at Rivos

Hsinchu City, Hsinchu City, Taiwan

Rivos Logo
Not SpecifiedCompensation
Mid-level (3 to 4 years)Experience Level
Full TimeJob Type
UnknownVisa
SemiconductorIndustries

Requirements

  • Bachelor's or Master's degree in EE/EECS with 4-7 years of relevant industry experience
  • 4 to 7 years of direct experience in power-aware design, including analysis, benchmarking, modeling, and simulation
  • Strong working knowledge of CPU architectures and workload modeling for power analysis (familiarity with RISC-V architecture is a significant plus)
  • Proficiency with Verilog and SystemVerilog RTL coding
  • Experience with the complete silicon design flow and evaluating power, performance, and area (PPA) trade-offs at the architectural, logic, and circuit levels
  • Hands-on experience with state-of-the-art EDA tools for gate-level and transistor-level power modeling and simulation
  • Strong scripting skills in Python, TCL, or other relevant languages
  • Proven ability to solve problems dynamically, innovate, drive decisions, and lead team efforts to deliver results under aggressive schedules

Responsibilities

  • Model and analyze power consumption for various workloads on custom silicon, working closely with the CPU Architecture, Performance, and Implementation teams to define overall power requirements
  • Analyze power and performance trade-offs, drive detailed cost-benefit analyses, and make recommendations for power reduction strategies
  • Collaborate with the Performance, Design Verification, and RTL teams to create targeted test vectors that model appropriate workloads and functionality scenarios for accurate simulation
  • Own the end-to-end power simulation process, including analysis, tuning, correlation, and presenting results to the Architecture, Logic Design, and Physical Design teams
  • Partner with the CAD and Physical Design teams to enhance power estimation methodologies, simulation flows, and regression analysis

Skills

Power Modeling
Power Analysis
CPU Architecture
RISC-V
Verilog
SystemVerilog
RTL Coding
PPA Optimization
Microarchitecture
Physical Implementation
Workload Modeling
Power Simulation
Silicon Design Flow

Rivos

Develops custom RISC-V server solutions

About Rivos

Rivos develops high-performance and power-efficient server solutions using RISC-V, an open-source hardware instruction set architecture. Their custom hardware is designed to meet the specific needs of enterprise clients, including data centers and cloud service providers, who require reliable systems for extensive data processing and storage. Rivos stands out in the competitive server market by utilizing RISC-V technology, which allows for greater flexibility and customization compared to traditional proprietary solutions. This enables Rivos to offer tailored and cost-effective products. The company generates revenue by selling specialized servers and may also provide related services like hardware support and consulting. Rivos aims to address the unique demands of high-performance computing environments while ensuring security and efficiency.

Santa Clara, CaliforniaHeadquarters
2021Year Founded
$243.2MTotal Funding
SERIES_ACompany Stage
Consulting, Hardware, Enterprise SoftwareIndustries
201-500Employees

Benefits

Flexible Work Hours

Risks

Potential legal challenges from established chip manufacturers like Intel and AMD.
Pressure from investors for quick returns may affect long-term strategies.
Geopolitical risks from international expansion, such as opening an office in Taiwan.

Differentiation

Rivos leverages RISC-V for customizable, open-source server solutions.
Focus on power-efficient, high-performance servers sets Rivos apart in the data center market.
Rivos' development of an open software stack enhances its competitive edge.

Upsides

Growing interest in RISC-V boosts Rivos' market potential in AI and data analytics.
Energy-efficient computing trends align with Rivos' power-efficient server solutions.
Rivos' recent $250M funding supports expansion into AI and data analytics markets.

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