Senior Emulation Validation Engineer at Astera Labs

San Jose, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, AI Infrastructure, Cloud ComputingIndustries

Requirements

BS/MS in Electrical Engineering, Computer Engineering or related field
5+ years of hands-on experience in pre-silicon validation using the emulation platforms (Palladium and/or Zebu)
Strong hands-on experience in running and debugging SOC simulation and emulation platforms
Protocol knowledge in high-speed protocols like PCIe, UALink and/or Ethernet is essential
Proficiency in programming and scripting languages (System Verilog, C/C++, Python)
Strong debugging and analytical skills
Excellent communication skills and ability to work independently with minimal supervision
Currently based locally or open to relocation
Experience in PCIe switch architectures, networking engine/packet processors, SOC peripheral protocols is a plus

Responsibilities

Play a key role in developing complex SOCs for AI connectivity and cloud infrastructures
Bring up and validate these SOCs using the industry standard emulation platforms (Palladium and Zebu)
Bring up and validate high-speed serial interfaces such as PCIe, Ethernet and UALink, and overall SoC functionality
Verify the SOC peripheral interfaces I2C/JTAG/SPI/UART etc
Collaborate closely with Architecture, Design, Verification, and SW/FW teams to define and execute functional/performance validation plans
Develop C/C++ FW and tests to validate and execute all test plan items
Build tools and methodologies to validate and debug all HW and SW/FW issues on the emulation platform

Skills

Key technologies and capabilities for this role

PalladiumZebuPCIeEthernetUALinkI2CJTAGSPIUARTC++SOC EmulationPre-silicon Validation

Questions & Answers

Common questions about this position

What is the base salary range for this position?

The base salary range is $175,000 USD - $195,000 USD, determined based on location, experience, and pay of employees in similar positions.

Is this role remote or does it require relocation?

Candidates must be currently based locally or open to relocation.

What are the key required skills for this role?

Required skills include 5+ years of hands-on experience in pre-silicon validation using emulation platforms like Palladium and Zebu, protocol knowledge in PCIe, UALink, and/or Ethernet, and proficiency in System Verilog, C/C++, and Python.

What is the company culture like at Astera Labs?

Astera Labs values diverse ideas, backgrounds, and experiences, actively encouraging applications from people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities to foster creativity and innovation.

What makes a strong candidate for this Senior Emulation Validation Engineer role?

Strong candidates have a BS/MS in Electrical Engineering or related field, 5+ years in emulation validation with Palladium/Zebu, expertise in high-speed protocols like PCIe and Ethernet, proficiency in System Verilog/C/C++/Python, and strong debugging skills.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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