Principal Engineer, Power Generation System
Kairos PowerInternship
Senior (5 to 8 years)
San Jose, California, United States
Key technologies and capabilities for this role
Common questions about this position
The role requires 8-10 years of experience in power and board design engineering, with a focus on ASIC or high-speed digital designs.
Proficiency in Cadence OrCAD and Allegro for schematic capture and PCB layout is required, along with a strong understanding of power integrity.
A Bachelor’s or Master’s degree in electrical engineering or a related field is required.
You will work closely with cross-functional teams, including firmware, mechanical, and validation engineers, to integrate designs into complete systems.
Candidates with 8-10 years of experience in power and board design for ASICs, proficiency in Cadence tools, strong power integrity knowledge, and experience evaluating power components and collaborating with vendors stand out.
Semiconductor connectivity solutions for AI infrastructure
Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.