Principal Digital Design Engineer at Astera Labs

Bengaluru, Karnataka, India

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Not SpecifiedCompensation

Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, AI, Cloud InfrastructureIndustries

Requirements

Bachelor’s in Electronics/Electrical engineering (Master's preferred)
12+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation
Proven expertise in RTL development, synthesis, and timing closure
Experience with front-end design, gate-level simulations, and design verification
Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude
Hands-on experience with processor IP (ARM/ARC)
Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART
Hands-on experience with complex DMA engines and FW interaction
Strong proficiency in System Verilog/Verilog and scripting (Python/Perl)
Experience with block-level and full-chip design at advanced nodes (≤ 16nm)
Silicon bring-up and post-silicon debug experience
Familiarity with Synopsys/Cadence tools and UVM-based design verification

Responsibilities

Design and implement high-performance digital solutions, including RTL development and synthesis
Collaborate with cross-functional teams on IP integration for processor IPs and peripherals
Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind
Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes ≤ 16nm
Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug
Utilize tools from Synopsys/Cadence and apply expertise in UVM-based verification flows

Skills

Key technologies and capabilities for this role

RTLSynthesisTiming ClosureUVMSynopsysCadencePCIeCXLEthernetIP IntegrationProcessor DesignSilicon DebugGDS

Questions & Answers

Common questions about this position

What salary can I expect for the Principal Digital Design Engineer role?

This information is not specified in the job description.

Is this Principal Digital Design Engineer position remote or office-based?

This information is not specified in the job description.

What key skills are required for the Principal Digital Design Engineer role?

Required skills include 12+ years of digital design experience with 4+ years in processor, peripherals and full chip implementation, proven expertise in RTL development, synthesis, and timing closure, hands-on experience with processor IP (ARM/ARC), and strong proficiency in System Verilog/Verilog and scripting (Python/Perl).

What is the company culture like at Astera Labs?

This information is not specified in the job description.

What makes a strong candidate for the Principal Digital Design Engineer position?

A strong candidate has a Bachelor’s in Electronics/Electrical engineering (Master's preferred), 12+ years of digital design experience including processor IP and peripherals, expertise in RTL, synthesis, timing closure, and advanced nodes ≤16nm, plus a strong work ethic and proactive attitude.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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