Power Optimization Engineer at Etched.ai

Cupertino, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

Experience in power optimization using dynamic voltage and frequency scaling techniques, power aware synthesis, glitch power reduction techniques as well as efficient power delivery network implementation
Experience with gate-level power optimization through VCD-based and/or FSDB-based power analysis
Strong understanding of concepts of energy consumption, estimation, data movement, low power design, and power-saving features
Digital design and optimization using industry-standard power analysis tools and methodologies
Leading power optimization at RTL and layout level using PrimePower, VCD-based analysis, DVFS, clock power reduction, clock gating, and glitch reduction techniques

Responsibilities

Develop chip power model from chip architecture, estimate chip power from microarchitecture, and devise power saving techniques for product use cases
Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to implement design for optimal power using advanced power management techniques
Estimate and analyze power consumption data at both full-chip and unit levels, guiding ASIC teams to enhance the power efficiency of all functional units both pre-silicon and post silicon. Correlate the estimated power consumption to the measured power

Skills

Key technologies and capabilities for this role

DVFSpower aware synthesisglitch power reductionVCD analysisFSDB analysisPrimePowerRTL optimizationclock gatingpower delivery networkpower estimation

Questions & Answers

Common questions about this position

What benefits are offered for this position?

Benefits include full medical, dental, and vision packages with 100% of premiums covered, a $2,000/month housing subsidy for those living within walking distance of the office, daily lunch and dinner in the office, and relocation support for those moving to Cupertino.

Is this role remote or onsite?

The position is onsite and the team is fully in-person in Cupertino.

What skills are required for the Power Optimization Engineer role?

Required experience includes power optimization using dynamic voltage and frequency scaling, power aware synthesis, glitch power reduction, efficient power delivery networks, gate-level power optimization through VCD/FSDB-based analysis, and strong understanding of energy consumption, estimation, data movement, low power design, and power-saving features.

What is the company culture like at Etched?

Etched is a fully in-person team in Cupertino that greatly values engineering skills, has no boundaries between engineering and research, and expects all technical staff to contribute to both as needed.

What makes a strong candidate for this role?

Strong candidates have experience with digital design and optimization using industry-standard power analysis tools, leading power optimization at RTL and layout levels with tools like PrimePower, VCD-based analysis, DVFS, clock power reduction, clock gating, and glitch reduction techniques.

Etched.ai

Develops servers for transformer inference

About Etched.ai

The company specializes in developing powerful servers for transformer inference, utilizing transformer architecture integrated into their chips to achieve highly efficient and advanced technology. The main technologies used in the product are transformer architecture and advanced chip integration.

Cupertino, CA, USAHeadquarters

2022Year Founded

$5.4MTotal Funding

SEEDCompany Stage

HardwareIndustries

11-50Employees