Front-End Power Engineer at Etched.ai

Cupertino, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

Experience in RTL development using Verilog/SystemVerilog, with a focus on low-power RTL design and optimization for complex digital systems
In-depth knowledge and experience in implementing low-power techniques like clock gating, power gating, and dynamic voltage/frequency scaling (DVFS)
Familiarity with synthesis and place-and-route processes with an emphasis on optimizing for power
UPF/CPF power intent specifications
Power analysis tools such as Synopsys PrimePower, Cadence Joules, or similar
Automation of power analysis and optimization workflows using scripting languages (Tcl, Perl, Python)

Responsibilities

Optimize RTL designs to boost power efficiency while meeting performance and area objectives
Perform power analysis throughout various stages of silicon design, applying power-saving strategies in RTL such as clock gating, power gating, multi-voltage domains, and dynamic voltage scaling
Conduct power estimation and evaluate PPA trade-offs for both new and existing design features
Collaborate closely with the physical design team to ensure power targets are met during the synthesis, place-and-route (P&R), and sign-off phases
Create precise power models from RTL simulations and gate-level netlists, and perform power roll-up analysis to estimate chip-level power consumption under different conditions

Skills

Key technologies and capabilities for this role

VerilogSystemVerilogClock GatingPower GatingMulti-Voltage DomainsDynamic Voltage ScalingDVFSUPFCPFSynopsys PrimePowerCadence JoulesTclPerlPythonRTLSynthesisPlace-and-Route

Questions & Answers

Common questions about this position

Is this position remote or onsite?

The position is onsite in Cupertino.

What benefits are offered for this role?

Benefits include full medical, dental, and vision packages with 100% of premiums covered, a $2,000/month housing subsidy for those living within walking distance of the office, daily lunch and dinner in the office, and relocation support for those moving to Cupertino.

What skills are required for the Front-End Power Engineer role?

Required skills include experience in RTL development using Verilog/SystemVerilog with a focus on low-power design, in-depth knowledge of low-power techniques like clock gating, power gating, and DVFS, and familiarity with synthesis and place-and-route processes emphasizing power optimization.

What is the company culture like at Etched?

Etched is a fully in-person team in Cupertino that greatly values engineering skills, has no boundaries between engineering and research, and expects all technical staff to contribute to both.

What makes a strong candidate for this position?

Strong candidates will have experience with UPF/CPF power intent specifications, power analysis tools like Synopsys PrimePower or Cadence Joules, and automation skills using scripting languages such as Tcl, Perl, or Python, in addition to the core requirements.

Etched.ai

Develops servers for transformer inference

About Etched.ai

The company specializes in developing powerful servers for transformer inference, utilizing transformer architecture integrated into their chips to achieve highly efficient and advanced technology. The main technologies used in the product are transformer architecture and advanced chip integration.

Cupertino, CA, USAHeadquarters

2022Year Founded

$5.4MTotal Funding

SEEDCompany Stage

HardwareIndustries

11-50Employees