DFT ATPG Engineer at d-Matrix

Bengaluru, Karnataka, India

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Not SpecifiedCompensation

Mid-level (3 to 4 years), Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field
5+ years of experience with DFT technologies, including scan test and MBIST
Experience with a hardware description language such as Verilog, System Verilog, or VHDL
Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.)
Ability to work well in a diverse team environment
Experience delivering detailed technical documentation
Experience with state-of-the-art industry-standard DFT tools
Hands-on experience in ATPG coverage analysis

Responsibilities

Partitioning for ATPG and hierarchical approaches
ATPG compression and serialization
RTL-Scan insertion and design rule fixing
STA constraints, Primetime execution, and timing exception flow
Interfacing with ASIC design teams to ensure DFT design rules and coverages are met
Generating high-quality manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression techniques
Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations
Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE
Responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE
Defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs

Skills

Key technologies and capabilities for this role

ATPGDFXDFTRTL Scan insertionSTAPrimetimeASIC designstuck-at faulttransition faultATPG compressionhierarchical ATPG

Questions & Answers

Common questions about this position

What is the work location and arrangement for this role?

The position is hybrid, requiring onsite work at the Bengaluru, Karnataka headquarters 3-5 days per week.

What is the salary for this DFT ATPG Engineer position?

This information is not specified in the job description.

What are the minimum qualifications and key skills required?

Candidates need a BE/ME in Electronic Engineering, Computer Science, or related field, 5+ years of experience with DFT technologies including scan test and MBIST, experience with HDLs like Verilog or SystemVerilog, and scripting languages like Perl.

What is the company culture like at d-Matrix?

The culture emphasizes respect, collaboration, humility, direct communication, inclusivity, and diverse perspectives for better solutions, while seeking passionate individuals driven by execution.

What makes a strong candidate for this DFT ATPG Engineer role?

Strong candidates have 5+ years in DFT with scan test and MBIST, hands-on experience with ATPG tools, HDLs like Verilog, scripting, and the ability to handle partitioning, compression, RTL scan insertion, STA, and interfacing with design teams.

d-Matrix

AI compute platform for datacenters

About d-Matrix

d-Matrix focuses on improving the efficiency of AI computing for large datacenter customers. Its main product is the digital in-memory compute (DIMC) engine, which combines computing capabilities directly within programmable memory. This design helps reduce power consumption and enhances data processing speed while ensuring accuracy. d-Matrix differentiates itself from competitors by offering a modular and scalable approach, utilizing low-power chiplets that can be tailored for different applications. The company's goal is to provide high-performance, energy-efficient AI inference solutions to large-scale datacenter operators.

Santa Clara, CaliforniaHeadquarters

2019Year Founded

$149.8MTotal Funding

SERIES_BCompany Stage

Enterprise Software, AI & Machine LearningIndustries

201-500Employees

Benefits

Hybrid Work Options

Risks

Competition from Nvidia, AMD, and Intel may pressure d-Matrix's market share.

Complex AI chip design could lead to delays or increased production costs.

Rapid AI innovation may render d-Matrix's technology obsolete if not updated.

Differentiation

d-Matrix's DIMC engine integrates compute into memory, enhancing efficiency and accuracy.

The company offers scalable AI solutions through modular, low-power chiplets.

d-Matrix focuses on brain-inspired AI compute engines for diverse inferencing workloads.

Upsides

Growing demand for energy-efficient AI solutions boosts d-Matrix's low-power chiplets appeal.

Partnerships with companies like Microsoft could lead to strategic alliances.

Increasing adoption of modular AI hardware in data centers benefits d-Matrix's offerings.

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