Senior Physical Design Engineer at Astera Labs

Santa Clara, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Cloud Infrastructure, Networking, AIIndustries

Requirements

Bachelor’s degree in Electrical Engineering (EE) or Computer Engineering required; Master’s degree preferred
≥3 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
Professional attitude with ability to prioritize multiple tasks, plan for customer meetings, and work with minimal guidance
Entrepreneurial, open-minded behavior and can-do attitude, thinking and acting fast with customer in mind
Proven expertise in developing/maintaining timing constraints, timing signoff methodology, and timing closure at block and full-chip level
Hands-on knowledge of synthesis, place and route, timing, extraction, formal verification (equivalence), and other backend tools/methodologies for 7nm or less technologies
Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production
Experience with Cadence and/or Synopsys physical design tools/flows
Familiarity and working knowledge of System Verilog/Verilog
Experience with DFT tools and techniques
Experience working with IP vendors for RTL and hard-macro blocks
Good scripting skills in Tcl, Python, or Perl

Responsibilities

Oversee planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs
Work closely with designers, verification engineering, and engineering operations

Skills

Key technologies and capabilities for this role

STATiming ConstraintsTiming SignoffTiming ClosureSynthesisPlace and RouteExtractionASIC DesignSoC DesignPhysical Design

Questions & Answers

Common questions about this position

What is the salary for the Senior Physical Design Engineer position?

This information is not specified in the job description.

Is this role remote or on-site?

This role is fully on-site and in-person.

What are the key required skills for this position?

Key required skills include proven expertise in timing constraints and closure, hands-on knowledge of synthesis, place and route, timing analysis for 7nm or less technologies, experience with Cadence/Synopsys tools, and scripting in Tcl, Python, or Perl.

What is the company culture like at Astera Labs?

The culture values entrepreneurial, open-minded behavior, a can-do attitude, thinking and acting fast with the customer in mind, and diverse teams with varied backgrounds and experiences.

What makes a strong candidate for this Senior Physical Design Engineer role?

Strong candidates have a Bachelor’s or Master’s in EE/Computer Engineering, ≥3 years supporting complex SoCs for server/storage/networking, full-chip/block ownership to GDSII, experience with IP vendors, and a professional attitude with minimal supervision needs.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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