Senior Physical Design Engineer at Normal Computing

London, England, United Kingdom

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

Experience of multiple aspects of SOC implementation through to tapeout - able to discuss personal examples of block layout, IP integration such as padrings, and global clock tree/bus layout
Strong familiarity with digital design flows for SOCs
Strong understanding of Synthesis, PNR and STA including timing signoff configuration
Experienced in configuring decks for, and driving the execution of, physical verification tools from block level to SOC
Fluency in Verilog and/or SystemVerilog
Experience in scripting languages Python and TCL
Excellent communication skills and the ability to work well on a small, interdisciplinary team
What Elevates Your Application
Proficiency with the Cadence suite of physical design tools, including Virtuoso, Genus, Innovus, Quantus, Tempus and Voltus
Experience mentoring or managing junior engineers
Experience with asynchronous logic
Experience developing digital design flows
Experience with foundries & foundry aggregators to help acquire, set up, and support PDKs, set up and perform LVS and DRC flows, and tape out a completed silicon product
Experience selecting, installing and evaluating EDA solutions
Experience selecting, sourcing, and integrating third-party IP from multiple different vendors into a silicon product
Familiarity with the wafer test, packaging, and chip testing process
Experience working at a startup

Responsibilities

Play a key role in the entire development process of our silicon, from idea to architecture to implementation to tape-out
Lead physical implementation of the SOC and all blocks
Own key aspects of SOC implementation flow development
Perform full chip signoff - including timing checks, power analysis, logical equivalence checking, EM/IR analysis, and physical verification
Contribute new ideas for potential thermodynamic computing technology implementations and architectures
Floorplan a complex SoC with analog, digital, and mixed-signal blocks
Drive requirements for and support analog layouts
Participate in the tape-out, bring-up, and testing of Normal’s silicon

Skills

Key technologies and capabilities for this role

SOC FloorplanningPNRSTAPhysical VerificationSynthesisTiming SignoffPower AnalysisEM/IR AnalysisVerilogSystemVerilogPythonTCLIP IntegrationClock TreeAnalog Layout

Questions & Answers

Common questions about this position

Is this position remote or hybrid?

The position is hybrid.

What skills are required for this Senior Physical Design Engineer role?

Required skills include experience with SOC implementation through tapeout, strong familiarity with digital design flows for SOCs, understanding of Synthesis, PNR and STA including timing signoff, experience with physical verification tools, fluency in Verilog/SystemVerilog, scripting in Python and TCL, and excellent communication skills for small teams.

What is the salary or compensation for this role?

This information is not specified in the job description.

What is the team environment like at Normal Computing?

You will work closely with the silicon and hardware R&D team on a small, interdisciplinary team.

What makes a strong candidate stand out for this position?

Candidates with experience in SOC implementation through tapeout, able to discuss personal examples of block layout and IP integration, plus strong technical skills in digital flows, scripting, and communication will be a great fit; proficiency in Cadence tools, mentoring experience, and foundry work elevate applications.

Normal Computing

Develops generative AI for enterprises

About Normal Computing

Normal Computing develops generative AI specifically for critical enterprise applications, focusing on large-scale enterprises like Fortune 500 companies in sectors such as semiconductor manufacturing, supply chain management, banking, and government. Their technology, based on Probabilistic AI, utilizes statistical analysis to predict outcomes, allowing businesses to have greater control over the reliability, adaptivity, and auditability of their AI models. This approach addresses the significant risks that have hindered AI adoption in these industries. Unlike many competitors, Normal Computing tailors its AI solutions to meet the specific needs of its clients, operating on a subscription or contract basis. The goal of Normal Computing is to mitigate risks associated with AI implementation, making it a more viable option for critical applications in high-stakes environments.

New York City, New YorkHeadquarters

2022Year Founded

$80.7MTotal Funding

GRANTCompany Stage

Enterprise Software, AI & Machine LearningIndustries

51-200Employees

Benefits

Flexible Work Hours

Risks

Competition from IBM and Intel in thermodynamic computing could challenge market position.

Global semiconductor shortages may impact hardware scaling capabilities.

AI regulatory changes in the EU and US could increase compliance costs.

Differentiation

Normal Computing uses Probabilistic AI for reliable, adaptive enterprise applications.

Their thermodynamic computer enhances AI reliability and efficiency, a first in the industry.

Founded by ex-Google Brain and X engineers, they have a strong AI development pedigree.

Upsides

Selected for ARIA's £50M Scaling Compute Program, boosting funding and visibility.

Raised $8.5M in seed funding to advance Probabilistic AI technology.

Growing demand for AI solutions in risk-averse industries like banking and government.

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