Principal Physical Design Engineer (STA) at Astera Labs

San Jose, California, United States

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Not SpecifiedCompensation

Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Networking, Cloud Infrastructure, Data CenterIndustries

Requirements

Bachelor's degree in Electrical Engineering (EE) or Computer Science required; Master's degree preferred
≥12 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
Proven expertise in developing/maintaining timing constraints, timing signoff methodology, and timing closure at the block and full-chip level
Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less
Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production
Experience with Cadence and/or Synopsys physical design tools/flows
Familiarity and working knowledge of System Verilog/Verilog
Experience with DFT tools and techniques
Experience in working with IP vendors for both RTL and hard-macro blocks
Good scripting skills in Tcl, Python, or Perl
Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision
Entrepreneurial, open-minded behavior and a can-do attitude. Think and act fast with the customer in mind

Responsibilities

Driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs
Working closely with designers, verification engineering, and engineering operations

Skills

Key technologies and capabilities for this role

Static Timing AnalysisTiming ConstraintsTiming SignoffTiming ClosureSynthesisPlace and RouteExtractionFormal VerificationPCIeCXLEthernetASICSoC

Questions & Answers

Common questions about this position

What is the base salary range for this Principal Physical Design Engineer role?

The base salary range is USD 209,000.00 – USD 250,000.00, determined based on location, experience, and pay of employees in similar positions.

Is this role remote or on-site?

This role is fully on-site and in-person.

What are the key required skills and experience for this position?

Required skills include proven expertise in timing constraints, signoff methodology, and closure; hands-on knowledge of synthesis, place and route, timing, extraction, formal verification for 7nm or less technologies; full chip or block level ownership to GDSII; experience with Cadence/Synopsys tools, System Verilog/Verilog, DFT, IP vendors, and scripting in Tcl, Python, or Perl. ≥12 years’ experience with complex SoC/silicon for Server, Storage, or Networking is needed.

What is the work environment and team collaboration like at Astera Labs?

You will work closely with designers, verification engineering, and engineering operations to drive the design of connectivity ASICs.

What makes a strong candidate for this Principal Physical Design Engineer role?

Strong candidates have a bachelor's in EE/CS (master's preferred), ≥12 years in complex SoC for server/storage/networking, expertise in STA and physical design tools for advanced nodes, full-chip ownership experience, plus an entrepreneurial, open-minded can-do attitude with the ability to prioritize tasks and work independently.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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