Physical Design Engineer V (IC)

Responsibilities include designing integrated chips by estimating die area, floor planning, placing memory, planning power, placing components, building clocks, and routing. The role involves designing and developing sign-off flows for static timing analysis, IR/EM, and physical verification to validate designs against product specifications. Additionally, the engineer will design and develop chip implementation and place and route flows using TCL/PERL, develop functional ECOs for design modifications, and design internal standard cell placement and routing connections for millions of instances. The engineer will also develop synthesis flows to convert RTL to foundry-specific netlists, including DFT insertion, and analyze synthesis results, providing feedback to the design team. A key responsibility is interfacing between the client and the India team for smooth project execution.