Lead Design Verification Engineer - CXL/PCIe at Astera Labs

Bengaluru, Karnataka, India

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Data Center, NetworkingIndustries

Requirements

Minimum of 6 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications
Strong academic and technical background in Electrical Engineering or Computer Engineering (Bachelor’s degree required, Master’s preferred)
Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance
Knowledge of industry-standard simulators, revision control systems, and regression systems
Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction
Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments
Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above
Ability to independently develop test plans and sequences in UVM to generate stimuli
Experience writing assertions, cover properties, and analyzing coverage data
Developing VIP abstraction layers for sequences to simplify and scale verification deployments
(Preferred) Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC
(Preferred) Experience with buffering and queuing with QoS on complex NOC-based SoCs
(Preferred) Analyzing performance at the system level on switching fabrics

Responsibilities

Develop and execute block-level and system-level verification plans
Write and execute test sequences, and collect and close coverage
Collaborate with RTL designers to debug failures and refine verification processes
Utilize coding and protocol expertise to contribute to functional verification
Develop user-controlled random constraints in transaction-based verification methodologies
Write assertions, cover properties, and analyze coverage data
Create VIP abstraction layers for sequences to simplify and scale verification deployments

Skills

Key technologies and capabilities for this role

PCIeCXLRTLUVMAssertionsCoverageVIPSystemVerilogSoC VerificationTransaction-Based Verification

Questions & Answers

Common questions about this position

What experience level is required for this role?

A minimum of 6 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications is required.

What are the key required skills for this position?

Key skills include interpreting PCIe/CXL protocol specifications, experience with third-party Verification IPs for PCIe/CXL Gen3 or above, developing test plans and sequences in UVM, writing assertions and cover properties, and developing VIP abstraction layers.

What is the salary range for this Lead Design Verification Engineer role?

This information is not specified in the job description.

Is this position remote or does it require office work?

This information is not specified in the job description.

What makes a strong candidate for this role?

Strong candidates have 6+ years in SoC verification for server/storage/networking, expertise in PCIe/CXL protocols and UVM, a degree in Electrical or Computer Engineering (Master’s preferred), plus an entrepreneurial mindset, professional attitude, and customer focus.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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