Director Digital Design Engineer at Astera Labs

San Jose, California, United States

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Not SpecifiedCompensation

Expert & Leadership (9+ years), Senior (5 to 8 years)Experience Level

Full TimeJob Type

NoVisa

Semiconductors, Networking, AI InfrastructureIndustries

Requirements

Bachelor’s degree in Electrical or Computer Engineering required; Master’s degree preferred
12+ years of experience developing or supporting complex SoC/silicon products for server, storage, or networking applications
5+ years of technical leadership or engineering management experience
Strong professional presence with the ability to manage multiple priorities, prepare for and lead customer discussions, and operate independently with minimal supervision
Entrepreneurial, open-minded, and action-oriented mindset with a strong customer focus
Authorized to work in the U.S. and able to start immediately
Hands-on experience and strong working knowledge of Ethernet or UALink
Solid understanding of packet-based switching architectures and network protocol processing
Proven experience with switch fabrics, crossbar architecture, and high-speed memory subsystems
Familiarity with high-speed interconnect protocols such as Ethernet, UALink, Infinity Fabric, NVLink, or HyperTransport
Strong front-end design expertise including architecture, RTL development, simulation, synthesis, timing closure, GLS, and DFT
Demonstrated ownership of full-chip or block-level development from architecture through GDS, delivering multiple complex designs into production, working closely with both hardware and software teams
Experience with Cadence and/or Synopsys digital design and DFT tool flows
Knowledge of DFT methodologies, including stuck-at and transition fault scan insertion
Expertise in silicon bring-up, performance tuning, and lab-based debug using equipment such as logic analyzers, scopes, protocol analyzers, and high-speed test setups
Experience working with advanced technology nodes (5nm or below)
Proficiency in scripting languages such as Python or equivalent (preferred)
Experience developing or supporting PCIe, Ethernet, or DDR-based products; familiarity with security-related standards (preferred)
Background in developing ASIC design methodologies and driving methodology adoption across teams (preferred)
Requires on-site presence

Responsibilities

Lead the microarchitecture, RTL implementation, and front-end development of high-performance connectivity solutions for next-generation network controllers

Skills

Key technologies and capabilities for this role

RTLmicroarchitectureASIC designPCIeEthernetUALinkSoCswitch fabricscrossbar architecturepacket-based switchingnetwork protocol processingCXL

Questions & Answers

Common questions about this position

Is this role remote or does it require on-site work?

This role requires on-site presence.

What are the basic qualifications for this position?

Candidates need a Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred), 12+ years of experience with complex SoC/silicon products for server, storage, or networking, and 5+ years of technical leadership or engineering management.

What key technical experiences are required?

Required experience includes hands-on knowledge of Ethernet or UALink, understanding of packet-based switching architectures, proven work with switch fabrics and high-speed memory subsystems, front-end design expertise from architecture through GDS, and experience with advanced nodes like 5nm or below.

What salary or compensation does this role offer?

This information is not specified in the job description.

What makes a strong candidate for this Director role?

A strong candidate has deep expertise in front-end ASIC design, strong leadership experience, solid understanding of protocols like PCIe, Ethernet, and UALink, plus an entrepreneurial, open-minded, action-oriented mindset with strong customer focus and the ability to manage priorities independently.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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