Digital Design Engineer

Candidates should possess a B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field, with a minimum of 2-3 years of experience in digital design. Required skills include RTL coding with SystemVerilog, debugging hardware in a lab environment using standard benchtop equipment, and a solid understanding of ASIC design flows (RTL design, synthesis, timing closure, verification). Experience with digital simulation tools (e.g., Xcelium, Questa, Vivado Simulator) and FPGA development using Xilinx tools (Vivado, ISE) is essential. Proficiency in scripting languages such as Python, TCL, or Perl for automation and testing is also required. Strong digital design fundamentals, hardware debugging skills, excellent analytical and debugging capabilities, effective communication and documentation habits, and a proactive, detail-oriented approach to work are necessary. Experience with post-silicon validation and debug of PMICs or mixed-signal ICs, and familiarity with standard cell libraries and digital integration in mixed-signal environments are considered helpful.