ATE Test Engineer (Silicon Validation) at Etched.ai

San Jose, California, United States

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$150,000 – $275,000Compensation

Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductor, AI HardwareIndustries

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
5+ years of hands-on experience developing and deploying wafer sort and final test programs for advanced node semiconductors (7nm or below)
Deep expertise with industry-standard ATE platforms (Teradyne UltraFLEX, Advantest V93000, or similar) and test program development environments
Proven track record managing wafer sort for large die sizes, understands power and thermal limitations and mitigations on tester
Strong knowledge of advanced process technologies and their test requirements
Experience with DFT methodologies including scan, ATPG, MBIST, and JTAG/boundary scan
Proficiency in test program debugging, failure analysis correlation, and yield enhancement techniques
Solid understanding of semiconductor manufacturing flow from wafer fab through final test

Responsibilities

Lead the development of comprehensive wafer sort and final test programs for large-format chips on advanced process nodes
Develop test patterns for structural tests (scan, MBIST, LBIST), functional tests, and parametric measurements at wafer and package levels
Architect and optimize test flows to balance test time, coverage, and yield learning objectives for complex AI accelerator designs
Manage relationships with test vendors and foundry partners to ensure test program portability and manufacturability
Drive root cause analysis of yield detractors using wafer probe data, final test data, failure analysis results, and statistical analysis techniques
Establish test data infrastructure for real-time monitoring of wafer sort and final test KPIs and predictive yield analytics
Interface with production team to ensure smooth transition from engineering wafer sort to high-volume manufacturing

Skills

Key technologies and capabilities for this role

Silicon ValidationWafer SortFinal Package TestingScan TestingMBISTLBISTDFTTest Pattern DevelopmentYield AnalysisStatistical AnalysisASIC TestingAI AcceleratorTest Data Infrastructure

Questions & Answers

Common questions about this position

What is the salary range for the ATE Test Engineer position?

The salary range is $150K - $275K.

Is this role remote or onsite?

This is an onsite position.

What key skills and experience are required for this role?

Candidates need 5+ years of hands-on experience developing wafer sort and final test programs for advanced node semiconductors (7nm or below), deep expertise with ATE platforms like Teradyne UltraFLEX or Advantest V93000, strong knowledge of DFT methodologies including scan, ATPG, MBIST, and JTAG, and experience managing wafer sort for large die sizes.

What is the company culture like at Etched.ai?

This information is not specified in the job description.

What makes a strong candidate for this ATE Test Engineer role?

Strong candidates have a Bachelor's or Master's in Electrical Engineering or related field, 5+ years experience with wafer sort and final test programs on 7nm or below nodes, expertise in ATE platforms and DFT, and experience with large die sizes; additional experience leading test program development for AI chips is ideal.

Etched.ai

Develops servers for transformer inference

About Etched.ai

The company specializes in developing powerful servers for transformer inference, utilizing transformer architecture integrated into their chips to achieve highly efficient and advanced technology. The main technologies used in the product are transformer architecture and advanced chip integration.

Cupertino, CA, USAHeadquarters

2022Year Founded

$5.4MTotal Funding

SEEDCompany Stage

HardwareIndustries

11-50Employees