ASIC Timing Engineer at Etched.ai

Cupertino, California, United States

Apply Now

Not SpecifiedCompensation

Mid-level (3 to 4 years), Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years of experience, or MS (or equivalent experience) with 2+ years of experience in Timing and STA
Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA)/Fishtail, Lint, CDC, RDC checks, and timing convergence
Expertise in analyzing and fixing timing paths through ECOs, with a focus on crosstalk and noise analysis
In-depth knowledge of RTL to Netlist, industry-standard STA and timing convergence tools
Familiarity with deep sub-micron process nodes, including modeling and converging timing in these nodes
Background in domain-specific STA and timing convergence, particularly with GPUs, CPUs, DPUs/Network processors, or SoCs
Experience in methodology and/or flow development, as well as automation

Responsibilities

Drive timing analysis and closure of chips at block, cluster, and full chip level
Collaborate with various teams to develop timing closure strategies and ensure timing and power convergence
Enhance timing convergence flows
Contribute to DFT timing closure
Work on timing closure of digital logic/macros

Skills

Key technologies and capabilities for this role

STAFishtailLintCDCRDCECOscrosstalk analysisnoise analysisRTL to NetlistDFTBISTAMS designstiming closuredeep sub-micron process nodes

Questions & Answers

Common questions about this position

What is the salary for the ASIC Timing Engineer position?

This information is not specified in the job description.

Is this ASIC Timing Engineer role remote or onsite?

The position is onsite.

What are the key skills required for the ASIC Timing Engineer role?

The role requires hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), expertise in analyzing and fixing timing paths through ECOs with focus on crosstalk and noise, in-depth knowledge of RTL to Netlist and industry-standard STA tools, familiarity with deep sub-micron process nodes, and experience in methodology and flow development.

What is the work environment like at Etched?

Etched is an innovative team building AI chips hard-coded for model architectures, focusing on high-performance demands and collaboration with teams like Physical Design, DFX, and Clocks.

What makes a strong application for the ASIC Timing Engineer position?

Candidates with BS/MS in Electrical or Computer Engineering and relevant experience in Timing and STA (5+ years for BS, 2+ for MS) are sought; apply even if you don't meet every qualification.

Etched.ai

Develops servers for transformer inference

About Etched.ai

The company specializes in developing powerful servers for transformer inference, utilizing transformer architecture integrated into their chips to achieve highly efficient and advanced technology. The main technologies used in the product are transformer architecture and advanced chip integration.

Cupertino, CA, USAHeadquarters

2022Year Founded

$5.4MTotal Funding

SEEDCompany Stage

HardwareIndustries

11-50Employees