Sr. ASIC Design Verification Engineer
GroqFull Time
Senior (5 to 8 years)
Key technologies and capabilities for this role
Common questions about this position
The position is hybrid, requiring onsite work at the Bangalore offices 3 days per week.
Candidates need a BS in Electrical Engineering, Computer Science, or related field with 7+ years of industry experience, or an MS with 5+ years preferred, plus experience in SoC verification cycle and verification methodologies like UVM/OVM.
Required skills include hands-on ASIC-SoC design verification tests and debug experience, fluency with SystemVerilog randomization constraints, coverage, and assertions, and good experience with SystemVerilog and UVM/OVM/VMM.
The culture emphasizes respect, collaboration, humility, direct communication, inclusiveness, transparency, intellectual honesty, and having fun while learning, with a focus on diverse perspectives for better solutions.
Strong candidates have good problem-solving skills, passion for AI challenges, experience thriving in a fast-paced startup, and preferably experience with C/C++, SystemC, and leading SoC verification environments to tape-out.
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