Senior Member of Technical Staff | #93121 at Rivos

Austin, Texas, United States

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

SemiconductorsIndustries

Requirements

Master’s or foreign equivalent in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field
3 years of experience in the job offered or a related occupation
At least 1 year of prior work experience in owning partitions/blocks of an E-core CPU and taking them through the PnR flow to produce a manufacturable GDS
Experience analyzing and closing timing by implementing design changes and fine-tuning critical timing paths
Experience optimizing floor plans to minimize footprint area while maintaining electrical integrity
Experience performing physical (pin placement) and timing constraints for sub-block implementation
Experience designing, analyzing, and implementing high-frequency clock distribution networks at the block level
Experience owning flow updates and contributing to the automation of the PnR flow through scripting
Experience in full chip timing analysis and closure, including distributed timing analysis, ECO generation, and timing model generation

Responsibilities

Implement block-level subcomponents and their physical integration within an SoC
Perform RTL synthesis to generate Verilog netlists
Execute Place and Route (PnR) flow to produce manufacturable GDS files
Optimize floorplans for IP core and subsystem integration
Generate physical and timing constraints for sub-block implementation
Design, analyze, and implement high-frequency clock distribution networks
Design, analyze, and implement high-performance interfaces between SoC subsystems
Analyze and close timing by implementing design changes and fine-tuning critical timing paths
Run physical verification and implement fixes to satisfy design rules
Contribute to the automation of the PnR flow through scripting and metric collection
Perform distributed timing analysis, ECO generation, and timing model generation for SOC teams

Skills

Key technologies and capabilities for this role

RTL SynthesisVerilogPnRGDSFloorplanningIP IntegrationClock DistributionHigh-Speed InterfacesTiming AnalysisTiming ClosureECOScriptingPhysical DesignSoC Integration

Questions & Answers

Common questions about this position

What is the salary for this Senior Member of Technical Staff position?

This information is not specified in the job description.

Is this role remote or does it require office work?

This information is not specified in the job description.

What experience is required for this role?

Candidates need a Master’s in Electronics Engineering, Electrical Engineering, Computer Engineering, or related field, plus 3 years of experience including at least 1 year owning E-core CPU partitions through PnR flow to GDS, timing closure, floorplan optimization, clock distribution networks, and PnR automation scripting.

What does the company culture look like at Rivos?

This information is not specified in the job description.

What makes a strong candidate for this position?

Strong candidates have a Master’s degree in a relevant engineering field and at least 3 years of experience, with specific hands-on expertise in owning E-core CPU blocks through PnR to GDS, timing analysis and closure, floorplanning, clock networks, and scripting for flow automation.

Rivos

Develops custom RISC-V server solutions

About Rivos

Rivos develops high-performance and power-efficient server solutions using RISC-V, an open-source hardware instruction set architecture. Their custom hardware is designed to meet the specific needs of enterprise clients, including data centers and cloud service providers, who require reliable systems for extensive data processing and storage. Rivos stands out in the competitive server market by utilizing RISC-V technology, which allows for greater flexibility and customization compared to traditional proprietary solutions. This enables Rivos to offer tailored and cost-effective products. The company generates revenue by selling specialized servers and may also provide related services like hardware support and consulting. Rivos aims to address the unique demands of high-performance computing environments while ensuring security and efficiency.

Santa Clara, CaliforniaHeadquarters

2021Year Founded

$243.2MTotal Funding

SERIES_ACompany Stage

Consulting, Hardware, Enterprise SoftwareIndustries

201-500Employees

Benefits

Flexible Work Hours

Risks

Potential legal challenges from established chip manufacturers like Intel and AMD.

Pressure from investors for quick returns may affect long-term strategies.

Geopolitical risks from international expansion, such as opening an office in Taiwan.

Differentiation

Rivos leverages RISC-V for customizable, open-source server solutions.

Focus on power-efficient, high-performance servers sets Rivos apart in the data center market.

Rivos' development of an open software stack enhances its competitive edge.

Upsides

Growing interest in RISC-V boosts Rivos' market potential in AI and data analytics.

Energy-efficient computing trends align with Rivos' power-efficient server solutions.

Rivos' recent $250M funding supports expansion into AI and data analytics markets.

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