Principal Signal/Power Integrity Engineer at Astera Labs

Shanghai, Shanghai, China

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Not SpecifiedCompensation

Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

NoVisa

Semiconductor, AI, Networking, Data CenterIndustries

Requirements

Strong academic/technical background in electrical engineering; Bachelor’s required; Master’s preferred
10+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications
10+ years of hands-on high-speed SI/PI design, simulation, and measurement experience
Proven track record with defining hardware system constraints and high-speed technology roadmaps
Cross-functional design mentality with the silicon design community to develop systems
Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment
Proven track record solving problems independently, preferably as a tech lead
Entrepreneurial, open-minded behavior, and can-do attitude
Authorized to work in the US and start immediately
Familiar with SI and PI design challenges for PCIe Gen5/6 and/or 200/400G Ethernet PCB and interconnects
2D and 3D simulation experience with Cadence/Ansys/ADS/etc. toolsets
EM modeling of connector structures
High-speed SERDES channel simulation, and equalization
Expertise in multi-level and NRZ signaling, COM, BER, jitter analysis
Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc
Working knowledge of PCB fabrication limits and trade-offs
PI experience a bonus
Familiar with industry standards such as PCISIG, and IEEE802.3, especially Electrical sections
Working knowledge of key, high-speed design blocks such as PLLs, DFE, Tx EQ
Proficiency in using high-speed lab equipment such as BERT, Oscilloscope, and VNA
Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams
Inherent sense of urgency and accountability; ability to multi-task in a fast-paced environment

Responsibilities

Execute SI planning, design, modeling, simulation, and lab validation with various system configurations for connectivity products in AI and ML applications

Skills

Key technologies and capabilities for this role

Signal IntegrityPower IntegrityPCIe Gen5PCIe Gen6200G Ethernet400G EthernetPCB DesignInterconnects2D Simulation3D SimulationHigh-Speed DesignSoCSerDes

Questions & Answers

Common questions about this position

Is this position remote or onsite?

This position will be onsite.

What education and experience are required for this role?

A Bachelor’s degree in electrical engineering is required, with a Master’s preferred, along with 10+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications and 10+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.

What specific technical skills are needed for signal and power integrity work?

Required skills include familiarity with SI and PI design challenges for PCIe Gen5/6 and/or 200/400G Ethernet PCB and interconnects, 2D and 3D simulation experience with Cadence/Ansys/ADS/etc. toolsets, high-speed SERDES channel simulation, and proficiency in using high-speed lab equipment such as BERT, Oscilloscope, and VNA.

What is the company culture like at Astera Labs?

Astera Labs values diverse ideas, backgrounds, and experiences to foster creativity and innovation, along with a self-starting, professional, hands-on work ethic in a dynamic environment.

What makes a strong candidate for this Principal Signal/Power Integrity Engineer role?

Strong candidates have a proven track record solving problems independently as a tech lead, a cross-functional design mentality, entrepreneurial open-minded behavior, and a can-do attitude, with US work authorization and immediate availability.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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