Principal Physical Design Engineer at Astera Labs

Bengaluru, Karnataka, India

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Not SpecifiedCompensation

Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, NetworkingIndustries

Requirements

Strong academic and technical background in electrical engineering; Bachelor’s degree in EE/Computer Engineering required, Master’s degree preferred
≥10 years’ experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
Professional attitude with ability to prioritize dynamic tasks, prepare for customer meetings, and work with minimal guidance
Entrepreneurial, open-minded behavior and can-do attitude; think and act fast with customer in mind
Hands-on knowledge of synthesis, place and route, CTS, extraction, timing analysis/STA, physical verification, and backend tools/methodologies for 16nm or less (preferably 7nm or less)
Proven expertise in synthesis, timing closure, and formal verification (equivalence) at block and full-chip level
Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production
Experience with Cadence and/or Synopsys physical design tools/flows
Familiarity and working knowledge of System Verilog/Verilog
Experience with DFT tools and techniques
Experience working with IP vendors for RTL and hard-mac blocks
Good scripting skills in Python or Perl
(Preferred) Good knowledge of DFT, stuck-at and transition scan test insertion
(Preferred) Familiarity with DFT test coverage and debug
(Preferred) Familiarity with ECO methodologies and tools

Responsibilities

Ownership of full chip or block level physical design from architecture to GDSII
Driving multiple complex designs to production
Performing synthesis, place and route, CTS, extraction, timing analysis/STA, and physical verification
Achieving timing closure and formal verification at block and full-chip levels
Working with Cadence/Synopsys physical design tools/flows
Collaborating with IP vendors for RTL and hard-mac blocks
Implementing DFT tools and techniques

Skills

Key technologies and capabilities for this role

SynthesisPlace and RouteCTSSTAPhysical VerificationCadenceSynopsysSystemVerilogVerilogDFTPythonPerl

Questions & Answers

Common questions about this position

What is the salary for this Principal Physical Design Engineer position?

Your base salary will be determined based on your experience, and the pay of employees in similar positions.

Is this role remote or does it require working in an office?

This information is not specified in the job description.

What key skills and experience are required for this position?

Candidates need ≥10 years’ experience with complex SoC/silicon products, hands-on knowledge of synthesis, place and route, CTS, STA, physical verification for 16nm or less technologies, expertise in Cadence/Synopsys tools, and good scripting skills in Python or Perl.

What is the company culture like at Astera Labs?

The company values an entrepreneurial, open-minded behavior and can-do attitude, with a professional attitude focused on prioritizing tasks, preparing for customer meetings, and working with minimal supervision while thinking fast with the customer in mind. They actively encourage diverse ideas, backgrounds, and experiences from people of color, LGBTQ+, veterans, parents, and individuals with disabilities.

What makes a strong candidate for this Principal Physical Design Engineer role?

A strong candidate has a strong academic background in EE/Computer engineering (Bachelor’s required, Master’s preferred), full chip or block level ownership from architecture to GDSII, proven expertise in timing closure and formal verification, and experience with DFT tools, IP vendors, and advanced nodes like 7nm or less.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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