Principal ASIC Verification Engineer at Hewlett Packard Enterprise

This role is onsite with an expectation to primarily work from an HPE office in Sunnyvale, CA, and you'll be in the office 2 days per week.

The role requires 12+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.

Candidates need strong expertise in SystemVerilog and UVM methodology, deep understanding of randomization, constraints, functional coverage, and assertions (SVA), hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs, plus proficiency with simulation tools like Cadence Xcelium, Synopsys VCS, and Mentor Questa.

HPE's culture thrives on finding new and better ways to accelerate what’s next, values varied backgrounds, offers flexibility to manage work and personal needs, embraces bold moves together, and supports career growth.

A strong candidate has 12+ years in ASIC/SoC verification, expertise in SystemVerilog/UVM, and experience owning verification efforts; experience with networking ASICs or high-speed interconnects is a plus.