Post Silicon Validation Engineer
GroqFull Time
Mid-level (3 to 4 years), Senior (5 to 8 years)
Candidates should possess a Master’s Degree or Bachelor’s Degree with 3-5 years of experience, along with hands-on experience verifying digital logic portions of DDR/HBM memory subsystem designs. Knowledge of JEDEC specifications for LPDDRx/DDRx/HBMx and DDR DFI specifications and protocols is required, as is familiarity with Reliability, availability, and serviceability (RAS) features within memory subsystems.
The Memory Controller Verification Engineer will collaborate closely with architects and design teams to verify DDR and HBM memory subsystem features, working with third-party IP vendors to validate integration and custom features. They will develop test plans and testbenches, integrate and bring up VIPs such as DDR_PHY and DDR_Model, develop test stimulus, checkers, and scoreboards in SystemVerilog/UVM, debug and regression closure, and provide debug support to emulation and silicon-bring-up teams. The role also involves working with global teams to ensure successful verification efforts.
Develops custom RISC-V server solutions
Rivos develops high-performance and power-efficient server solutions using RISC-V, an open-source hardware instruction set architecture. Their custom hardware is designed to meet the specific needs of enterprise clients, including data centers and cloud service providers, who require reliable systems for extensive data processing and storage. Rivos stands out in the competitive server market by utilizing RISC-V technology, which allows for greater flexibility and customization compared to traditional proprietary solutions. This enables Rivos to offer tailored and cost-effective products. The company generates revenue by selling specialized servers and may also provide related services like hardware support and consulting. Rivos aims to address the unique demands of high-performance computing environments while ensuring security and efficiency.