Data Parallel Accelerator Post-Silicon Performance Lead at Rivos

Santa Clara, California, United States

Rivos Logo
Not SpecifiedCompensation
Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level
Full TimeJob Type
UnknownVisa
Semiconductors, HardwareIndustries

Requirements

  • Deep expertise in GP-GPU architecture and microarchitecture
  • Strong programming skills in C/C++ and Python
  • Solid understanding of ML/DL workloads and benchmarks; experience optimizing LLMs at the system level is a significant plus
  • Familiarity with SIMT processing, cache, and memory hierarchies
  • Hands-on experience with performance counters and profiling techniques
  • Knowledge of performance improvement concepts: bottleneck analysis, latency hiding, speculative execution, resource scheduling, buffer sizing, replacement policies
  • Experience with embedded systems (bare-metal testing/debugging is a plus)
  • Excellent teamwork, ownership, and communication skills; ability to thrive under aggressive schedules and adapt quickly
  • Bachelor’s degree with 12+ years of experience in a relevant field, or Master’s degree with 10+ years of experience in a relevant field, or PhD with 5+ years of experience in a relevant field

Responsibilities

  • Lead cross-functional performance validation: Analyze workloads and microbenchmarks in emulation and post-silicon environments, ensuring strong correlation with cycle-accurate models and RTL
  • System-level performance optimization: Measure and tune workloads (Generative AI, data analytics) for optimal performance per watt
  • Collaborate across teams: Work closely with design, architecture, systems, and software groups to enable enterprise use-case performance measurements
  • Power and performance correlation: Integrate silicon power measurements with simulation and full-chip projections to drive hardware/software tuning
  • Performance infrastructure automation: Develop and automate tools for performance measurement, debug, and reporting
  • Debug and tuning: Conduct system-level power and performance debugging, including silicon register tuning to meet aggressive performance targets
  • Drive innovation: Influence architectural decisions and validation methodologies to ensure our platforms remain at the forefront of the industry

Skills

Key technologies and capabilities for this role

Post-Silicon ValidationEmulationPerformance OptimizationRTL CorrelationPower AnalysisGenerative AIData AnalyticsFirmwareArchitectureCompiler OptimizationISA DesignVerification

Questions & Answers

Common questions about this position

What is the salary for this position?

This information is not specified in the job description.

Is this role remote or does it require being in Silicon Valley?

This information is not specified in the job description.

What skills are required for the Data Parallel Accelerator Post-Silicon Performance Lead role?

Required skills include deep expertise in GP-GPU architecture and microarchitecture, strong programming skills in C/C++ and Python, solid understanding of ML/DL workloads and benchmarks, familiarity with SIMT processing, cache, and memory hierarchies, hands-on experience with performance counters and profiling techniques, and knowledge of performance improvement concepts like bottleneck analysis.

What is the company culture like at Rivos?

Rivos offers a creative, collaborative, and flexible workplace that encourages exploration across the full hardware-software stack, where you'll collaborate with some of the world’s most talented engineers to push boundaries in performance, energy efficiency, programmability, and scalability.

What makes a strong candidate for this role?

A strong candidate has deep expertise in GP-GPU architecture, strong C/C++ and Python programming skills, experience with ML/DL workloads and performance optimization, and hands-on knowledge of profiling, debugging, and performance improvement techniques in post-silicon environments.

Rivos

Develops custom RISC-V server solutions

About Rivos

Rivos develops high-performance and power-efficient server solutions using RISC-V, an open-source hardware instruction set architecture. Their custom hardware is designed to meet the specific needs of enterprise clients, including data centers and cloud service providers, who require reliable systems for extensive data processing and storage. Rivos stands out in the competitive server market by utilizing RISC-V technology, which allows for greater flexibility and customization compared to traditional proprietary solutions. This enables Rivos to offer tailored and cost-effective products. The company generates revenue by selling specialized servers and may also provide related services like hardware support and consulting. Rivos aims to address the unique demands of high-performance computing environments while ensuring security and efficiency.

Santa Clara, CaliforniaHeadquarters
2021Year Founded
$243.2MTotal Funding
SERIES_ACompany Stage
Consulting, Hardware, Enterprise SoftwareIndustries
201-500Employees

Benefits

Flexible Work Hours

Risks

Potential legal challenges from established chip manufacturers like Intel and AMD.
Pressure from investors for quick returns may affect long-term strategies.
Geopolitical risks from international expansion, such as opening an office in Taiwan.

Differentiation

Rivos leverages RISC-V for customizable, open-source server solutions.
Focus on power-efficient, high-performance servers sets Rivos apart in the data center market.
Rivos' development of an open software stack enhances its competitive edge.

Upsides

Growing interest in RISC-V boosts Rivos' market potential in AI and data analytics.
Energy-efficient computing trends align with Rivos' power-efficient server solutions.
Rivos' recent $250M funding supports expansion into AI and data analytics markets.

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