Analog Design Engineer, Sr Staff/Principal at d-Matrix

Santa Clara, California, United States

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$196,000 – $300,000Compensation

Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

BS/MS/PhD in Electrical Engineering (preferred) with BS 15+/MS 10+/PhD 8+ years of related professional experience in high-speed circuit design blocks such as Phase Interpolator, Clocking, PLL designs
Experience and knowledge of Schematic Capture, Spice Simulations and running Monte-Carlo simulations
Experience and knowledge of Circuit Layout, Extraction and running back-annotated simulations
Experience with Channel modeling using Matlab or other tools
Participation and contribution in Standard bodies (plus)
Effective interpersonal and teamwork skills
Proficiency in working with cross functional and cross site teams
Excellent communication skills
Demonstrates good analysis and problem-solving skills
Ability to multi-task in a fast-paced environment

Responsibilities

Analog-mixed signal integrated circuit design using common circuit design tools from Cadence and Synopsys
Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out
Schematic circuit design
System level performance analysis
Design test benches for simulations and verifications
Guide layout engineers on layout in deep sub-micron process nodes from 4nm and below
Optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis
Independent minor layout tweaks when necessary
Work with backend engineers on integration of design/layout
Provide model of circuit for backend verification
Participate in Evaluation Board design for silicon bring-up and bench debug or characterization
Build scripts for silicon bring up and test features

Skills

Key technologies and capabilities for this role

CadenceSynopsysAnalog DesignMixed-Signal ICSchematic DesignPVT AnalysisMonte-Carlo SimulationDeep Sub-Micron LayoutDie-to-Die InterfaceIn-Memory ComputeSilicon Bring-UpVerificationHigh-Speed Circuits

Questions & Answers

Common questions about this position

What is the salary range for this Analog Design Engineer position?

The salary range is $196K - $300K.

Is this role remote or hybrid, and what's the location policy?

The position is hybrid, requiring onsite work at the Santa Clara, CA headquarters 3-5 days per week.

What key skills and experience are required for this role?

Candidates need a BS/MS/PhD in Electrical Engineering with 15+/10+/8+ years of experience in high-speed circuit design like Phase Interpolator, Clocking, and PLLs, plus proficiency in schematic capture, Spice and Monte-Carlo simulations, circuit layout, extraction, back-annotated simulations, and channel modeling with Matlab.

What is the company culture like at d-Matrix?

The culture emphasizes respect, collaboration, humility, direct communication, inclusivity, and diverse perspectives for better solutions, while seeking passionate individuals driven by execution.

What makes a strong candidate for this Sr Staff/Principal Analog Design Engineer role?

Strong candidates have advanced degrees in Electrical Engineering with extensive experience in high-speed analog design, proven skills in simulations and layout, effective teamwork, communication, problem-solving abilities, and the capacity to multi-task in a fast-paced environment; participation in standards bodies is a plus.

d-Matrix

AI compute platform for datacenters

About d-Matrix

d-Matrix focuses on improving the efficiency of AI computing for large datacenter customers. Its main product is the digital in-memory compute (DIMC) engine, which combines computing capabilities directly within programmable memory. This design helps reduce power consumption and enhances data processing speed while ensuring accuracy. d-Matrix differentiates itself from competitors by offering a modular and scalable approach, utilizing low-power chiplets that can be tailored for different applications. The company's goal is to provide high-performance, energy-efficient AI inference solutions to large-scale datacenter operators.

Santa Clara, CaliforniaHeadquarters

2019Year Founded

$149.8MTotal Funding

SERIES_BCompany Stage

Enterprise Software, AI & Machine LearningIndustries

201-500Employees

Benefits

Hybrid Work Options

Risks

Competition from Nvidia, AMD, and Intel may pressure d-Matrix's market share.

Complex AI chip design could lead to delays or increased production costs.

Rapid AI innovation may render d-Matrix's technology obsolete if not updated.

Differentiation

d-Matrix's DIMC engine integrates compute into memory, enhancing efficiency and accuracy.

The company offers scalable AI solutions through modular, low-power chiplets.

d-Matrix focuses on brain-inspired AI compute engines for diverse inferencing workloads.

Upsides

Growing demand for energy-efficient AI solutions boosts d-Matrix's low-power chiplets appeal.

Partnerships with companies like Microsoft could lead to strategic alliances.

Increasing adoption of modular AI hardware in data centers benefits d-Matrix's offerings.

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