SoC Top-Level Physical Design Engineer at Tenstorrent

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets, with the actual offer impacted by experience, skills, education, background, and location.

This role is hybrid, based out of Santa Clara, CA; Austin, TX; or Ft. Collins, CO.

The role requires 8+ years of top-level SOC physical design experience on complex, multi-million gate designs, along with deep expertise in hierarchical floorplanning, fabric implementation, power grid design, global clock distribution, bump planning, RDL implementation, multi-voltage domain designs, timing closure, EM/IR analysis, and physical verification at the chip level.

Tenstorrent values collaboration, curiosity, and a commitment to solving hard problems, with a diverse team of technologists passionate about AI and building the best AI platform.

Strong candidates are seasoned physical design engineers with expertise in full-chip implementation challenges, who excel at cross-disciplinary collaboration with architecture, RTL, and packaging teams, and are passionate about optimizing for power, performance, and area while driving design closure on aggressive schedules.