Sr. ASIC Design Verification Engineer
GroqFull Time
Senior (5 to 8 years)
Candidates should possess a Bachelor’s degree in Electrical Engineering with at least 3 years of experience, or a Master’s degree in Electrical Engineering with 1 year of experience. They must have strong knowledge of ASIC simulation tools and verification languages, including Verdi/Siloti, and fluency in verification languages such as UVM/OVM/System Verilog, Vera, and Verilog. Experience in writing test-plans and creating directed and random test cases is also required.
The Senior Verification Engineer will define verification architecture, implement verification environments for block-level, SoC subsystems, and SOC top-level design, utilizing advanced verification methodologies to meet established content, performance, quality, cost, and schedule goals. They will work with RTL designers, system architects, and block-level verification engineers to develop top-level verification requirements and test plans, analyze and debug simulation failures, generate code coverage and functional coverage reports, perform gate-level simulation, and run directed and random test cases.
Licenses high-performance semiconductor IP cores
Omni Design Technologies creates high-performance, ultra-low power IP cores for the semiconductor industry, which are essential for advanced systems on chips (SoCs) used in technologies like 5G, LiDAR, and AI. They license these IP cores to other companies, allowing for seamless integration into existing designs, which simplifies the development of complex mixed-signal SoCs. Their collaborations with companies like LeddarTech and MegaChips highlight their ability to enhance technologies in automotive and data conversion sectors. The goal of Omni Design is to empower various industries by providing reliable semiconductor solutions that drive technological innovation.