Model Risk Analyst III - Validation
M&T BankFull Time
Mid-level (3 to 4 years), Senior (5 to 8 years)
San Jose, California, United States
Key technologies and capabilities for this role
Common questions about this position
A Bachelor’s degree in electrical or computer engineering is required, with a Master’s preferred, along with at least 6 years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
Desired skills include strong knowledge in scripting for automation like Python or Matlab, experience with PAM4 SerDes validation (200G/100G/50G), high-speed SerDes protocols like Ethernet and PCIe, SerDes architecture, lab equipment such as protocol analyzers and scopes, and signal integrity tools.
This information is not specified in the job description.
This information is not specified in the job description.
Candidates should demonstrate a professional attitude with the ability to prioritize tasks, plan for meetings, work with minimal supervision, and exhibit entrepreneurial, open-minded behavior and a can-do attitude.
Semiconductor connectivity solutions for AI infrastructure
Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.