Senior Principal Physical Design Engineer at Astera Labs

San Jose, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, AI InfrastructureIndustries

Requirements

Master’s or PhD in Electrical or Electronics Engineering from a leading institute
10+ years of experience in physical design with multiple successful tapeouts at ≤5nm technology nodes
Strong hands-on expertise in floorplanning, placement, CTS, routing, timing, power analysis, and signoff
Proficiency with EDA tools such as Cadence Innovus, Synopsys FC, Calibre, Voltus, RedHawk
Demonstrated experience in implementing SerDes, PHYs, or high-bandwidth interconnects (e.g., PCIe, CXL)
Proven ability to collaborate across domains and lead technical efforts from spec to silicon
Preferred Qualifications
Experience with AI/ML SoC designs, chiplet architectures, or UCIe interfaces
Exposure to high-speed analog/mixed-signal integration and co-design
Familiarity with signal/power integrity considerations for high-performance computing
Contributions to patents, publications, or conference presentations in the field

Responsibilities

Lead and drive IP/macro block-level physical implementation from RTL to GDSII, focusing on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems
Architect implementation strategies for AI SoCs and chiplets, supporting complex clock/power domains and hierarchical floorplans
Collaborate with RTL, STA, DFT, packaging, and verification teams to ensure timing and physical convergence
Own advanced physical design tasks including: EM/IR and power grid optimization for high-current blocks, congestion mitigation and routing-aware floorplanning, RC-aware timing closure across corners and PVTs, clock tree synthesis and skew management across domains
Lead chiplet integration efforts with emphasis on die-to-die interfaces, timing alignment, and physical abstraction
Drive signoff closure: DRC, LVS, antenna, ERC, and tapeout readiness using industry-standard tools (e.g., Innovus, ICC2, Calibre, Voltus, RedHawk)
Contribute to and improve physical design automation infrastructure using Tcl, Python, Perl, and other scripting tools
Act as a technical mentor, reviewing designs, guiding junior engineers, and contributing to global technical leadership
Interface with EDA vendors and TSMC for tool qualification and design enablement

Skills

Key technologies and capabilities for this role

RTL-to-GDSIIPPA OptimizationSerDesClock Tree SynthesisEM/IRPower Grid OptimizationFloorplanningCongestion MitigationTiming ClosureSTADFTChiplet IntegrationDie-to-Die InterfacesHierarchical Design

Questions & Answers

Common questions about this position

What experience level is required for this role?

A Master’s or PhD in Electrical or Electronics Engineering from a leading institute and 10+ years of experience in physical design with multiple successful tapeouts at ≤5nm technology nodes are required.

What key technical skills and tools are needed?

Strong hands-on expertise in floorplanning, placement, CTS, routing, timing, power analysis, and signoff is required, along with proficiency in EDA tools such as Cadence Innovus, Synopsys FC, Calibre, Voltus, RedHawk.

What is the salary or compensation for this position?

This information is not specified in the job description.

Is this role remote or does it require working in an office?

This information is not specified in the job description.

What does the team structure look like and what mentoring is involved?

The role involves mentoring engineers across the global design team, collaborating with RTL, STA, DFT, packaging, and verification teams, and contributing to global technical leadership.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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