Sr. ASIC Design Verification Engineer
GroqFull Time
Senior (5 to 8 years)
Key technologies and capabilities for this role
Common questions about this position
This is a full-time position.
This information is not specified in the job description.
The role requires deep expertise in PCIe (Gen1–6), host interface subsystems, high-performance verification methodologies, UVM-based verification environments, and experience verifying complex IPs like PCIe Gen5/Gen6 controllers, DMA engines, and fabric interconnects.
The role involves providing technical leadership and mentorship to junior engineers, and coordinating across global verification teams, while collaborating with architecture, design, and post-silicon validation teams.
Candidates with highly experienced backgrounds in leading verification of complex IPs like PCIe Gen5/Gen6, architecting UVM environments, driving test plans to closure, providing technical leadership across global teams, and influencing verification strategy will stand out.
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