Sr. ASIC Design Verification Engineer
GroqSalary not specified
Full Time
Senior (5 to 8 years)
Principal Design Verification Engineer - CXL/PCIe at Astera Labs
Bengaluru, Karnataka, India
Not SpecifiedCompensation
Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level
Full TimeJob Type
UnknownVisa
Semiconductors, AI, Cloud Infrastructure, Data CentersIndustries
Requirements
- Minimum of 8 years’ experience in supporting or developing complex SoC/silicon products for server, storage, and/or networking applications
- Strong academic and technical background in Electrical Engineering or Computer Engineering (bachelor’s degree required, master’s preferred)
- Professional attitude with the ability to prioritize tasks, prepare for customer meetings, and work independently with minimal guidance
- Knowledge of industry-standard simulators, revision control systems, and regression systems
- Entrepreneurial, open-minded behavior and a can-do attitude, with a focus on customer satisfaction
- Interpreting PCIe/CXL standard protocol specifications to develop and execute verification plans in simulation environments
- Experience using Verification IPs from third-party vendors for PCIe/CXL, focusing on Gen3 or above
- Ability to independently develop test plans and sequences in UVM to generate stimuli
- Experience writing assertions, cover properties, and analyzing coverage data
- Developing VIP abstraction layers for sequences to simplify and scale verification deployments
- (Preferred) Expertise in verifying Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols, including compliance on PCIe/CXL EP/RC
- (Preferred) Experience with buffering and queuing with QoS on complex NOC-based SoCs
- (Preferred) Analyzing performance at the system level on switching fabrics
Responsibilities
- Develop and execute block-level and system-level verification plans
- Write and execute test sequences and collect and close coverage
- Collaborate with RTL designers to debug failures and refine verification processes
- Utilize coding and protocol expertise to contribute to functional verification
- Develop user-controlled random constraints in transaction-based verification methodologies
- Write assertions, cover properties, and analyze coverage data
- Create VIP abstraction layers for sequences to simplify and scale verification deployments
Skills
PCIe
CXL
Design Verification
Functional Verification
RTL
Assertions
Coverage Analysis
Transaction-Based Verification
VIP
SoC
Astera Labs
Semiconductor connectivity solutions for AI infrastructure
About Astera Labs
Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.
Santa Clara, CaliforniaHeadquarters
2017Year Founded
$200.8MTotal Funding
IPOCompany Stage
Data & Analytics, Hardware, AI & Machine LearningIndustries
201-500Employees