Post Silicon Validation Engineer
GroqFull Time
Mid-level (3 to 4 years), Senior (5 to 8 years)
Candidates should possess a Master’s Degree or Bachelor’s Degree with 3-5 years of experience in digital logic verification, specifically related to DDR/HBM memory subsystem designs. Strong knowledge of JEDEC specifications for LPDDRx, DDRx, and HBMx is required, along with familiarity with DDR DFI specification and protocol. Experience with Reliability, availability and serviceability (RAS) features within memory subsystems, including error detection/correction and encryption, is also desired.
As a Memory Controller Verification Engineer, you will collaborate closely with architects and design teams to verify the feature sets of DDR and HBM memory subsystem designs. You will work with third-party IP vendors to validate the correctness of integration and custom features, developing test plans and testbenches. This role involves integrating and bringing up VIPs such as DDR_PHY and DDR_Model, developing test stimulus, checkers, and scoreboards in SystemVerilog/UVM, and providing debug support to emulation and silicon-bring-up teams. Furthermore, you will debug, regression, and coverage closure, and be able to work effectively with teams across continents.
Develops custom RISC-V server solutions
Rivos develops high-performance and power-efficient server solutions using RISC-V, an open-source hardware instruction set architecture. Their custom hardware is designed to meet the specific needs of enterprise clients, including data centers and cloud service providers, who require reliable systems for extensive data processing and storage. Rivos stands out in the competitive server market by utilizing RISC-V technology, which allows for greater flexibility and customization compared to traditional proprietary solutions. This enables Rivos to offer tailored and cost-effective products. The company generates revenue by selling specialized servers and may also provide related services like hardware support and consulting. Rivos aims to address the unique demands of high-performance computing environments while ensuring security and efficiency.