Lead DFT Engineer (Design for Test) at Astera Labs

Bengaluru, Karnataka, India

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Not SpecifiedCompensation

Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

NoVisa

Semiconductor, AI InfrastructureIndustries

Requirements

Minimum of bachelor’s degree in computer engineering/electrical engineering, Masters preferred
Minimum 4+ years of experience in a semiconductor company as a DFT engineer
Must be local or willing to relocate
Chip design, Verilog and System Verilog
Verification, UVM methodology
ATPG tools
Scan insertion tools
Gate-level simulations
Static timing analysis
Scripting (Perl/Tcl)
Familiarity with ATE
Hands-on expertise with commercial test generation tools for large complex designs
Strong fundamental knowledge of DFT techniques including JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression
Experience running test compression software
Experience using the Mentor Tessent or Synopsys DFT Max and Tetramax tools
Preferred experience
Experience with defining and implementing SOC level verification on large designs
Working with 93k Tester
Experience with IEEE 1500 Standard or IEEE 1687 standard and MBIST, LBIST

Responsibilities

Part of the DFT Design team developing next generation connectivity products
Responsible for the full product life cycle, from definition to mass production to end of life
Work closely with all engineering teams, physical design, and functions like back-end testing, manufacturing, defect, and reliability analysis
Solve problems in a collaborative manner between multiple engineering teams

Skills

Key technologies and capabilities for this role

DFTVerilogSystemVerilogUVMATPGScan insertionJTAGScan compressionGate-level simulationsStatic timing analysisPerlTclATE

Questions & Answers

Common questions about this position

What is the salary for the Lead DFT Engineer position?

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

Is this position remote or does it require relocation?

Candidates must be local or willing to relocate.

What are the required skills for this DFT Engineer role?

Required skills include chip design with Verilog and System Verilog, verification using UVM methodology, ATPG tools, scan insertion tools, gate-level simulations, static timing analysis, scripting in Perl/Tcl, and hands-on expertise with commercial test generation tools for large designs.

What is the company culture like at Astera Labs?

The role requires a team-oriented approach with a focus on solving problems collaboratively across multiple engineering teams.

What makes a strong candidate for this Lead DFT Engineer position?

Strong candidates have a minimum of 4+ years of DFT experience in a semiconductor company, a bachelor's or master's in computer/electrical engineering, and expertise in DFT techniques like JTAG, ATPG, scan compression, plus preferred experience with SOC verification, IEEE standards, and specific testers.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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