FPGA Design Engineer, Staff at d-Matrix

Santa Clara, California, United States

d-Matrix Logo
$142,500 – $237,500Compensation
Senior (5 to 8 years), Junior (1 to 2 years)Experience Level
Full TimeJob Type
UnknownVisa
AI & Machine Learning, Hardware, Enterprise SoftwareIndustries

Skills

Key technologies and capabilities for this role

VerilogVHDLRISC-VPythonHardware Description LanguagesHardware-Software IntegrationFPGA DesignFPGA VerificationTest AutomationMCTPPLDMSPDMPlatform BMCPMBusSecure BootCloud Server Architectures

Questions & Answers

Common questions about this position

What is the salary range for the FPGA Design Engineer position?

The salary range is $142.5K - $237.5K.

Is this role remote or hybrid, and what are the location requirements?

This is a hybrid role requiring onsite presence at the Santa Clara, CA headquarters 3 days per week.

What key skills and experience are required for this FPGA Design Engineer role?

Requirements include 5+ years of FPGA design and verification experience, expertise in HDLs like Verilog or VHDL, familiarity with RISC-V architecture, and experience with scripting languages like Python. Additional needs cover hardware-software integration, industry-standard protocols (MCTP, PLDM, SPDM), BMC, power management, and hardware security.

What is the company culture like at d-Matrix?

The culture emphasizes respect, collaboration, humility, direct communication, and inclusivity, seeking passionate individuals who thrive in dynamic environments.

What makes a strong candidate for this FPGA Design Engineer role?

Strong candidates have a Bachelor’s or Master’s in Electrical/Computer Engineering, 5+ years in FPGA design/verification, expertise in HDLs and RISC-V, plus experience with protocols like MCTP/PLDM/SPDM, BMC, power management, security, and Python scripting, along with excellent problem-solving and teamwork skills.

d-Matrix

AI compute platform for datacenters

About d-Matrix

d-Matrix focuses on improving the efficiency of AI computing for large datacenter customers. Its main product is the digital in-memory compute (DIMC) engine, which combines computing capabilities directly within programmable memory. This design helps reduce power consumption and enhances data processing speed while ensuring accuracy. d-Matrix differentiates itself from competitors by offering a modular and scalable approach, utilizing low-power chiplets that can be tailored for different applications. The company's goal is to provide high-performance, energy-efficient AI inference solutions to large-scale datacenter operators.

Santa Clara, CaliforniaHeadquarters
2019Year Founded
$149.8MTotal Funding
SERIES_BCompany Stage
Enterprise Software, AI & Machine LearningIndustries
201-500Employees

Benefits

Hybrid Work Options

Risks

Competition from Nvidia, AMD, and Intel may pressure d-Matrix's market share.
Complex AI chip design could lead to delays or increased production costs.
Rapid AI innovation may render d-Matrix's technology obsolete if not updated.

Differentiation

d-Matrix's DIMC engine integrates compute into memory, enhancing efficiency and accuracy.
The company offers scalable AI solutions through modular, low-power chiplets.
d-Matrix focuses on brain-inspired AI compute engines for diverse inferencing workloads.

Upsides

Growing demand for energy-efficient AI solutions boosts d-Matrix's low-power chiplets appeal.
Partnerships with companies like Microsoft could lead to strategic alliances.
Increasing adoption of modular AI hardware in data centers benefits d-Matrix's offerings.

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