Sr. ASIC Design Verification Engineer
GroqFull Time
Senior (5 to 8 years)
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Common questions about this position
The salary range is $142.6k - $206.5k USD for Bay Area California only, with actual salary varying based on factors like job location, knowledge, skills, experience, and training. Incentive opportunities are also offered based on individual and company performance.
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Candidates need a BS/MS in Electrical Engineering, Computer Engineering or related field plus 12+ years of industry experience, including 12+ years developing verification in Verilog, SystemVerilog and UVM, 7 years with Ethernet/Security (MACSEC) protocol verification, 7 years UVM fluency, 7 years with complex coverage-driven random constraint UVM environments, and 7 years experience with high-level specs into test plans and debugging.
This information is not specified in the job description.
A strong candidate will have a BS/MS in Electrical Engineering or related field with 12+ years of experience, deep expertise in UVM, SystemVerilog, Verilog, Ethernet/Security protocol verification, complex coverage-driven UVM environments, test planning from specs, and strong debugging skills.
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