Senior Staff ASIC Design Verification Engineer
GroqSalary not specified
- Full Time
- Senior (5 to 8 years)
$150,000 – $275,000Compensation
Senior (5 to 8 years)Experience Level
Full TimeJob Type
UnknownVisa
AI & Machine Learning, Hardware, Robotics & AutomationIndustries
Requirements
Candidates must have at least 8 years of relevant experience developing scalable test benches and a proven understanding of the System Verilog testbench language. Experience with high-speed SerDes is required, along with a willingness to start quickly. A passion for modern AIs like ChatGPT and a desire to learn about them on the job are essential.
Responsibilities
The Design Verification Engineer will ensure shippable first silicon for Etched’s first ASIC and develop test benches for blocks and IP.
Skills
System Verilog
SerDes
Python
Verilator
HBM3
HBM3E
Machine Learning
Numerical Analysis
Etched.ai
Develops servers for transformer inference
About Etched.ai
The company specializes in developing powerful servers for transformer inference, utilizing transformer architecture integrated into their chips to achieve highly efficient and advanced technology. The main technologies used in the product are transformer architecture and advanced chip integration.
Key Metrics
Cupertino, CA, USAHeadquarters
2022Year Founded
$5.4MTotal Funding
SEEDCompany Stage
HardwareIndustries
11-50Employees