Strategic Sourcing Engineer, Silicon
Groq- Full Time
- Mid-level (3 to 4 years)
Candidates should possess a Bachelor’s degree in Electrical Engineering or Computer Engineering, along with 4-6 years of experience as a BE/LO engineer. They must demonstrate the ability to quickly adapt to new technologies and possess strong communication skills, coupled with a collaborative teamwork approach.
The Full Chip Layout Physical Design Engineer will be responsible for implementing and analyzing full chip layout, including partition groups and top-level designs, adhering to specifications and challenging constraints to optimize for area, route, and integration. This role involves resolving complex layout and congestion problems, participating in flows development, and performing DRC, LVS, and ANT checks at both partition group and full chip levels.
Designs GPUs and AI computing solutions
NVIDIA designs and manufactures graphics processing units (GPUs) and system on a chip units (SoCs) for various markets, including gaming, professional visualization, data centers, and automotive. Their products include GPUs tailored for gaming and professional use, as well as platforms for artificial intelligence (AI) and high-performance computing (HPC) that cater to developers, data scientists, and IT administrators. NVIDIA generates revenue through the sale of hardware, software solutions, and cloud-based services, such as NVIDIA CloudXR and NGC, which enhance experiences in AI, machine learning, and computer vision. What sets NVIDIA apart from competitors is its strong focus on research and development, allowing it to maintain a leadership position in a competitive market. The company's goal is to drive innovation and provide advanced solutions that meet the needs of a diverse clientele, including gamers, researchers, and enterprises.