Backend Engineer, Full Chip Layout

Position Overview

• Location Type: [Not specified]
• Employment Type: Full-time
• Salary: Not specified
• Description: NVIDIA is seeking best-in-class Full Chip Layout Physical Design Engineers to join their outstanding Networking Silicon engineering team. The team develops industry-leading high-speed communication devices, focusing on high throughput and low latency. This role involves implementing and analyzing chip layouts, resolving complex problems, and participating in flow development.

Requirements

• Education: B.SC. in Electrical Engineering or Computer Engineering
• Experience: 4-6 years of experience as a BE/LO Engineer
• Skills:
  • Ability to quickly adapt to new technology.
  • Strong communication skills.
  • Great teamwork skills.
  • Drive to develop new solutions for issues.

Responsibilities

• Full Chip Layout implementation and analysis of partition groups / top-level according to specifications.
• Addressing challenging constraints, targeting area, routing, and integration.
• Working on a variety of challenging designs (including high cell count and HS blocks).
• Resolving complex layout and congestion problems.
• Performing DRC, LVS, and ANT for partition groups and full chip level.
• Participating in flows development.

Ways to Stand Out

• Knowledge of physical design flows and methodologies (PNR, STA, physical verification).
• Familiarity with physical design EDA tools (Synopsys, Cadence, etc.).

Company Information

• Company: NVIDIA
• Description: NVIDIA is a technology-focused company with forward-thinking people. This role offers a meaningful, growing, and highly professional environment where you can make a significant impact.

Application Instructions

• [Not specified - Please refer to NVIDIA's career website for application instructions.]