ASIC Design Engineer at NVIDIA

The base salary range is 108,000 USD - 184,000 USD for Level 2, and 136,000 USD - 212,750 USD for Level 3, determined based on location, experience, and pay of employees in similar positions. You will also be eligible for equity and benefits.

This is a hybrid position.

Required qualifications include an MS/PhD in Electrical Engineering or Computer Engineering (or equivalent), 3+ years of relevant industry experience in high-speed coherent interconnects, protocol bridges, hardware-managed coherency and system level caches, experience with multiple clock domains and asynchronous interfaces, strong knowledge of Verilog or VHDL, and scripting like PERL. Knowledge of CHI/CXL/PCI-E and experience across the ASIC design flow including emulation, prototyping, DFT, timing analysis, floor planning, ECO, bringup & lab debug, and ATE test development are pluses.

NVIDIA features a dynamic, technology-focused environment with hard-working, forward-thinking engineers from around the globe pushing the frontiers of innovation in areas like AI and self-driving cars. They value creativity, autonomy, constant innovation, and fostering a diverse work environment.

Strong candidates have an MS/PhD in EE/CE, 3+ years in high-speed coherent interconnects and system caches, RTL design experience with Verilog/VHDL, and good communication skills. A history of mentoring juniors, knowledge of CHI/CXL/PCI-E, and full ASIC flow experience including emulation and debug are highly valued.