Validation Engineer, Staff - Post Silicon at d-Matrix

Santa Clara, California, United States

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$155,000 – $258,000Compensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, AIIndustries

Requirements

BS/MS in Electrical/Computer Engineering with 5+ years industry experience working with high performance SoC
Embedded software/firmware/RTOS development with 5+ years industry experience
Familiarity with high speed serial protocol (such as PCIe Gen3/4/5) and/or high speed external memory technology (such as LPDDR3/LPDDR4/LPDDR5 and/or high speed I/O standards)
Excellent debugging verbal and written communication skills
Capable of working effectively across cross functional organizational boundaries

Responsibilities

Work on chip(s) bring up, validation and debug of cutting-edge interference accelerator chiplet, including test and validate high-speed serial protocols like PCIe Gen5, high-speed memory interfaces such as LPDDR5, and die-to-die chiplet interconnect blocks
Create and implement comprehensive test bring-up and validation plans, develop automated randomization of software/firmware kernel functions and logging instrumentation in conjunction with self-checking post processors
Develop test scripts and embedded firmware functions for host systems that will test and validate aspects of high-speed interfaces, including PCIe, LPDDR, and D2D
Collaborate with team to procure and acquire the latest lab equipment
Work hand-in-hand with hardware, software, and operations teams on challenges such as ATE tests and hardware/software debugging

Skills

PCIe Gen5

LPDDR5

die-to-die interconnect

chip bring-up

validation

debugging

test scripts

embedded firmware

high-speed serial protocols

high-speed memory interfaces

firmware kernels

self-checking post processors

d-Matrix

AI compute platform for datacenters

About d-Matrix

d-Matrix focuses on improving the efficiency of AI computing for large datacenter customers. Its main product is the digital in-memory compute (DIMC) engine, which combines computing capabilities directly within programmable memory. This design helps reduce power consumption and enhances data processing speed while ensuring accuracy. d-Matrix differentiates itself from competitors by offering a modular and scalable approach, utilizing low-power chiplets that can be tailored for different applications. The company's goal is to provide high-performance, energy-efficient AI inference solutions to large-scale datacenter operators.

Santa Clara, CaliforniaHeadquarters

2019Year Founded

$149.8MTotal Funding

SERIES_BCompany Stage

Enterprise Software, AI & Machine LearningIndustries

201-500Employees

Benefits

Hybrid Work Options

Risks

Competition from Nvidia, AMD, and Intel may pressure d-Matrix's market share.

Complex AI chip design could lead to delays or increased production costs.

Rapid AI innovation may render d-Matrix's technology obsolete if not updated.

Differentiation

d-Matrix's DIMC engine integrates compute into memory, enhancing efficiency and accuracy.

The company offers scalable AI solutions through modular, low-power chiplets.

d-Matrix focuses on brain-inspired AI compute engines for diverse inferencing workloads.

Upsides

Growing demand for energy-efficient AI solutions boosts d-Matrix's low-power chiplets appeal.

Partnerships with companies like Microsoft could lead to strategic alliances.

Increasing adoption of modular AI hardware in data centers benefits d-Matrix's offerings.

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