Technical Lead Design Verification Engineer at Astera Labs

San Jose, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level

Full TimeJob Type

NoVisa

Semiconductors, Networking, Data Centers, AI, Cloud InfrastructureIndustries

Requirements

Strong academic and technical background in electrical engineering (minimum Bachelor’s in EE, Master’s preferred)
≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications
Knowledge of industry-standard simulators, revision control systems, and regression systems
Professional attitude with ability to prioritize multiple tasks, work with minimal guidance and supervision
Entrepreneurial, open-minded behavior and can-do attitude; think and act fast with customer in mind
Authorized to work in the US and start immediately
Experience with full verification lifecycle based on System Verilog/UVM/C/C++
Proven ability to mix and deploy hybrid techniques (directed and constrained random)
Experience with bug hunting, coverage hunting; formal methods a plus
Ability to work independently to develop test-plans and test-sequences, generate stimuli, and collaborate with RTL designers to debug failures
Ability to identify and write all types of coverage measures for stimulus and corner-cases, close coverage to identify verification holes

Responsibilities

Contribute to functional verification of designs using coding and problem-solving skills
Handle full lifecycle of verification: planning, writing tests, debugging, collecting and closing coverage
Work with software and system validation teams to develop test plans and execute them in emulation platforms
Develop hybrid mechanisms for verification of complex ASICs

Skills

SystemVerilog

C++

Python

ASIC Verification

SoC Verification

Functional Verification

Coverage Closure

Emulation

Scripting

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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