Sr. ASIC Design Verification Engineer
GroqSalary not specified
Full Time
Senior (5 to 8 years)
Technical Lead Design Verification Engineer at Astera Labs
San Jose, California, United States
Not SpecifiedCompensation
Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level
Full TimeJob Type
NoVisa
Semiconductors, Networking, Data Centers, AI, Cloud InfrastructureIndustries
Requirements
- Strong academic and technical background in electrical engineering (minimum Bachelor’s in EE, Master’s preferred)
- ≥5 years’ experience verifying and validating complex SoC for Server, Storage, and Networking applications
- Knowledge of industry-standard simulators, revision control systems, and regression systems
- Professional attitude with ability to prioritize multiple tasks, work with minimal guidance and supervision
- Entrepreneurial, open-minded behavior and can-do attitude; think and act fast with customer in mind
- Authorized to work in the US and start immediately
- Experience with full verification lifecycle based on System Verilog/UVM/C/C++
- Proven ability to mix and deploy hybrid techniques (directed and constrained random)
- Experience with bug hunting, coverage hunting; formal methods a plus
- Ability to work independently to develop test-plans and test-sequences, generate stimuli, and collaborate with RTL designers to debug failures
- Ability to identify and write all types of coverage measures for stimulus and corner-cases, close coverage to identify verification holes
Responsibilities
- Contribute to functional verification of designs using coding and problem-solving skills
- Handle full lifecycle of verification: planning, writing tests, debugging, collecting and closing coverage
- Work with software and system validation teams to develop test plans and execute them in emulation platforms
- Develop hybrid mechanisms for verification of complex ASICs
Skills
Key technologies and capabilities for this role
Questions & Answers
Common questions about this position
What is the salary for this Technical Lead Design Verification Engineer position?
This information is not specified in the job description.
Is this position remote or does it require working from an office?
This information is not specified in the job description.
What skills are required for this role?
Required skills include experience with the full verification lifecycle using System Verilog/UVM/C/C++, ability to deploy hybrid directed and constrained random techniques, coverage measures for stimulus and corner-cases, and working independently to develop test-plans while collaborating with RTL designers.
What is the company culture like at Astera Labs?
The culture emphasizes entrepreneurial, open-minded behavior, a can-do attitude, thinking and acting fast with the customer in mind, and a professional attitude with the ability to prioritize tasks and work with minimal supervision.
What makes a strong candidate for this position?
Strong candidates have a Bachelor’s in EE (Master’s preferred), ≥5 years verifying complex SoCs for Server/Storage/Networking, experience with System Verilog/UVM, hybrid verification techniques, coverage closure, and are authorized to work in the US and able to start immediately.
Astera Labs
Semiconductor connectivity solutions for AI infrastructure
About Astera Labs
Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.
Santa Clara, CaliforniaHeadquarters
2017Year Founded
$200.8MTotal Funding
IPOCompany Stage
Data & Analytics, Hardware, AI & Machine LearningIndustries
201-500Employees