Senior/Staff Formal Verification Engineer at Untether AI

Candidates should possess a Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering, along with at least 3 years of proven experience in formal verification, specifically Formal Property Verification. They must have hands-on experience with formal verification tools like Cadence JasperGold or Synopsys VC Formal, and demonstrate expertise in SystemVerilog Assertions (SVAs). A solid understanding of RTL design using Verilog or VHDL, combined with knowledge of digital design principles, is also required. Furthermore, candidates should have a decent understanding of compute architecture, including CPU, GPU, or specialized AI hardware accelerators, and the ability to verify performance, timing, and functional properties within these architectures. Proficiency in scripting languages, particularly Python, for automation and tool integration is essential.