Sr. ASIC Design Verification Engineer
GroqFull Time
Senior (5 to 8 years)
Key technologies and capabilities for this role
Common questions about this position
The position requires 6+ years of experience with complex ASIC designs and/or verification.
Candidates need familiarity with System Verilog language, experience with UVM verification methodology, and formal verification methods. Experience with CPU architecture and standard I/O interfaces like Ethernet, PCIe, USB, DDR, or HBM is a plus.
The primary location is Bengaluru, Karnataka, India.
This information is not specified in the job description.
Strong communication skills, the ability to work with a team spread across different geography sites, and flexibility in a dynamic environment are required.
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